Simulation Results: rv_timer

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.14 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 87.94 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.730s 57.277us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.650s 61.890us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.650s 45.466us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.210s 255.569us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.660s 15.779us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.680s 16.580us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.650s 45.466us 1 1 100.00
rv_timer_csr_aliasing 0.660s 15.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.850s 484.635us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.040s 452.808us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 170.910s 945632.785us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 170.910s 945632.785us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.010s 14685.514us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 14.621us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.590s 37.267us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.800s 505.569us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.800s 505.569us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 61.890us 1 1 100.00
rv_timer_csr_rw 0.650s 45.466us 1 1 100.00
rv_timer_csr_aliasing 0.660s 15.779us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 58.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 61.890us 1 1 100.00
rv_timer_csr_rw 0.650s 45.466us 1 1 100.00
rv_timer_csr_aliasing 0.660s 15.779us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 58.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.720s 77.243us 1 1 100.00
rv_timer_tl_intg_err 0.760s 153.766us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.760s 153.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.610s 64.372us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.600s 857.007us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 7.260s 782.496us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 103349243041143209391675977307990780119180809065212209744136832843778141369025 82
UVM_INFO @ 64371850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 32026798305317617013100386230004662169253757259301221457415976636339075767473 82
UVM_INFO @ 484635347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 8346193762715855838654519326637701207677855431606544625776127315295910893050 81
UVM_INFO @ 857006966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 98181636131148503453838174477254204591303341778540670213115535143706480101828 183
UVM_INFO @ 782496045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---