Simulation Results: spi_device/1r1w

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.17 %
  • code
  • 90.87 %
  • assert
  • 95.15 %
  • func
  • 69.49 %
  • line
  • 98.85 %
  • branch
  • 98.20 %
  • cond
  • 95.78 %
  • toggle
  • 74.30 %
  • FSM
  • 87.23 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 41.730s 14856.911us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.970s 23.436us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.610s 101.016us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.010s 2363.043us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.200s 2084.280us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.950s 145.188us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.610s 101.016us 1 1 100.00
spi_device_csr_aliasing 6.200s 2084.280us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.620s 10.849us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.780s 133.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.770s 20.201us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.680s 2.889us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.670s 6.606us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.880s 16.865us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.880s 16.865us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.070s 340.752us 1 1 100.00
spi_device_tpm_sts_read 0.960s 28.162us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 27.760s 8245.649us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.360s 2231.505us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.190s 3351.229us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.190s 3351.229us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.090s 565.590us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.090s 565.590us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.090s 565.590us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.090s 565.590us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.090s 565.590us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 11.110s 13656.599us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 9.640s 1233.892us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 9.640s 1233.892us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 9.640s 1233.892us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.490s 190.699us 1 1 100.00
spi_device_read_buffer_direct 3.730s 963.640us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 9.640s 1233.892us 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 10.320s 5378.136us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.950s 1142.664us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.950s 1142.664us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 0.850s 18.641us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 41.730s 14856.911us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 271.680s 95285.103us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 168.240s 25691.557us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.800s 35.834us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.700s 35.734us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.370s 33.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.370s 33.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 23.436us 1 1 100.00
spi_device_csr_rw 2.610s 101.016us 1 1 100.00
spi_device_csr_aliasing 6.200s 2084.280us 1 1 100.00
spi_device_same_csr_outstanding 2.830s 112.187us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 23.436us 1 1 100.00
spi_device_csr_rw 2.610s 101.016us 1 1 100.00
spi_device_csr_aliasing 6.200s 2084.280us 1 1 100.00
spi_device_same_csr_outstanding 2.830s 112.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.960s 65.233us 1 1 100.00
spi_device_tl_intg_err 11.180s 766.769us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.180s 766.769us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 80936507584549377966608975977311030226906625833844314723123017609924770732547 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2148837 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2148837 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[959])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 94315972503726177319242154009819814320438106169928382980777880962337026048269 76
UVM_ERROR @ 4136843 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3a9 [1110101001] vs 0x0 [0])
UVM_ERROR @ 4173843 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x17e [101111110] vs 0x0 [0])
UVM_ERROR @ 4212843 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf [1111] vs 0x0 [0])
UVM_ERROR @ 4295843 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x26b [1001101011] vs 0x0 [0])