Simulation Results: sram_ctrl/main

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.44 %
  • code
  • 94.91 %
  • assert
  • 97.82 %
  • func
  • 93.60 %
  • block
  • 95.08 %
  • line
  • 95.71 %
  • branch
  • 92.21 %
  • toggle
  • 91.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 693.958us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 25.056us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.604us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 211.617us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.454us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1575.154us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.604us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.454us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 239.000s 82299.617us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 38.000s 963.521us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 18.000s 14849.267us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 173.000s 5242.394us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 121.000s 4474.414us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 25.000s 6622.393us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 17.000s 6111.672us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 31.000s 49579.331us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1404.663us 1 1 100.00
sram_ctrl_partial_access_b2b 307.000s 25863.812us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 706.897us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 3182.645us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 2674.999us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 16.000s 4655.197us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 350.807us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 48.000s 40525.797us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.807us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 251.577us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 251.577us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 25.056us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.604us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.454us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 14.200us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 25.056us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.604us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.454us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 14.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 10.000s 3736.261us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1313.221us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 1156.109us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1313.221us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 1156.109us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 16.000s 4655.197us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 16.000s 4655.197us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.604us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 31.000s 49579.331us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 31.000s 49579.331us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 31.000s 49579.331us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 17.000s 6111.672us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 700.405us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 10.000s 3736.261us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 964.009us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 693.958us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 693.958us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 31.000s 49579.331us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1313.221us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 17.000s 6111.672us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1313.221us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1313.221us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 693.958us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1313.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.000s 557.516us 1 1 100.00