Simulation Results: sysrst_ctrl

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.06 %
  • code
  • 88.48 %
  • assert
  • 87.64 %
  • func
  • 67.07 %
  • line
  • 94.85 %
  • branch
  • 95.70 %
  • cond
  • 92.22 %
  • toggle
  • 100.00 %
  • FSM
  • 59.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.540s 2129.488us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.610s 2456.472us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.060s 2425.503us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.680s 2527.861us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.770s 4065.270us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.720s 2034.863us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 30.880s 31351.551us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.600s 2619.634us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.960s 2223.325us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.720s 2034.863us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.600s 2619.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 36.290s 132228.077us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 49.860s 53862.885us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 4.250s 3142.021us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.790s 3804.751us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.550s 2546.085us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.530s 2235.809us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.470s 2975.482us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.800s 2630.120us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.600s 3958.197us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 34.120s 35072.402us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.820s 8471.483us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.440s 2035.428us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.160s 2026.415us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.540s 2104.567us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.540s 2104.567us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.770s 4065.270us 1 1 100.00
sysrst_ctrl_csr_rw 3.720s 2034.863us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.600s 2619.634us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.680s 8819.310us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.770s 4065.270us 1 1 100.00
sysrst_ctrl_csr_rw 3.720s 2034.863us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.600s 2619.634us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.680s 8819.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 6.750s 22192.697us 1 1 100.00
sysrst_ctrl_tl_intg_err 12.070s 22459.596us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 12.070s 22459.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.990s 3050.784us 1 1 100.00