Simulation Results: uart

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.17 %
  • code
  • 90.50 %
  • assert
  • 98.27 %
  • func
  • 45.74 %
  • line
  • 98.86 %
  • branch
  • 96.27 %
  • cond
  • 92.18 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.910s 447.321us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.700s 14.538us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.640s 97.223us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.860s 316.768us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.690s 76.170us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.730s 26.702us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.640s 97.223us 1 1 100.00
uart_csr_aliasing 0.690s 76.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 62.390s 44271.889us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.910s 447.321us 1 1 100.00
uart_tx_rx 62.390s 44271.889us 1 1 100.00
parity_error 2 2 100.00
uart_intr 6.290s 7513.601us 1 1 100.00
uart_rx_parity_err 26.850s 27315.374us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 62.390s 44271.889us 1 1 100.00
uart_intr 6.290s 7513.601us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 92.650s 138464.195us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 49.570s 47079.171us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 11.220s 11965.265us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 6.290s 7513.601us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 6.290s 7513.601us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 6.290s 7513.601us 1 1 100.00
perf 1 1 100.00
uart_perf 93.610s 7002.619us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.380s 5204.407us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.380s 5204.407us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.770s 6950.102us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 7.170s 7421.149us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.870s 922.610us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.070s 5419.658us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 254.230s 69459.916us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 11.620s 154819.532us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.580s 13.456us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.610s 57.041us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.650s 77.840us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.650s 77.840us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.700s 14.538us 1 1 100.00
uart_csr_rw 0.640s 97.223us 1 1 100.00
uart_csr_aliasing 0.690s 76.170us 1 1 100.00
uart_same_csr_outstanding 0.740s 28.029us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.700s 14.538us 1 1 100.00
uart_csr_rw 0.640s 97.223us 1 1 100.00
uart_csr_aliasing 0.690s 76.170us 1 1 100.00
uart_same_csr_outstanding 0.740s 28.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.940s 85.588us 1 1 100.00
uart_tl_intg_err 1.160s 78.932us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.160s 78.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 39.670s 4839.779us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 60553441822803857902825406912589236046285857946556203538292501883817328180786 81
UVM_ERROR @ 5300977550 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5300977550 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 6014427702 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 14, clk_pulses: 0
UVM_ERROR @ 6014594370 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (138 [0x8a] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_stress_all_with_rand_reset 40588223052780301842967089647968917098898200221019387308244651569812918398638 171
UVM_ERROR @ 3013286082 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3013286082 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 3064537176 ps: (cip_base_vseq__tl_errors.svh:301) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/504
UVM_ERROR @ 3102714978 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all 44959518913184963625745041800150381303218870144652477266677574214174585222661 86
UVM_ERROR @ 150764156604 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 150764281604 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (195 [0xc3] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 153610906604 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 30, clk_pulses: 0
UVM_ERROR @ 153611156604 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty