Simulation Results: adc_ctrl

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.70 %
  • code
  • 96.83 %
  • assert
  • 96.92 %
  • func
  • 18.36 %
  • line
  • 99.05 %
  • branch
  • 98.45 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.280s 6015.346us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.000s 1045.030us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.370s 457.922us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 52.500s 34137.167us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.280s 919.577us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.960s 645.070us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.370s 457.922us 1 1 100.00
adc_ctrl_csr_aliasing 2.280s 919.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 76.510s 53565.398us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 6.530s 36190.641us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 25.620s 19721.404us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 2.160s 17615.385us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 33.380s 46939.291us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 33.490s 24814.982us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 9.800s 60317.677us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 5.870s 25479.558us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.490s 3556.444us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 18.300s 28220.921us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 66.390s 77872.691us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 47.750s 43097.486us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.650s 308.024us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.070s 489.494us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.270s 416.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.270s 416.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.000s 1045.030us 1 1 100.00
adc_ctrl_csr_rw 1.370s 457.922us 1 1 100.00
adc_ctrl_csr_aliasing 2.280s 919.577us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.230s 3741.395us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.000s 1045.030us 1 1 100.00
adc_ctrl_csr_rw 1.370s 457.922us 1 1 100.00
adc_ctrl_csr_aliasing 2.280s 919.577us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.230s 3741.395us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.470s 4120.078us 1 1 100.00
adc_ctrl_tl_intg_err 12.620s 8019.759us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 12.620s 8019.759us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 2.650s 1482.620us 1 1 100.00