Simulation Results: aes/masked

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.67 %
  • code
  • 94.17 %
  • assert
  • 98.23 %
  • func
  • 73.61 %
  • block
  • 94.31 %
  • line
  • 95.89 %
  • branch
  • 87.26 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 105.815us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 85.305us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 85.178us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 55.002us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 373.248us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 71.926us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 142.913us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 55.002us 1 1 100.00
aes_csr_aliasing 2.000s 71.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 85.305us 1 1 100.00
aes_config_error 2.000s 78.528us 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 85.305us 1 1 100.00
aes_config_error 2.000s 78.528us 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 148.530us 1 1 100.00
aes_b2b 6.000s 994.476us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 85.305us 1 1 100.00
aes_config_error 2.000s 78.528us 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
aes_alert_reset 4.000s 781.040us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 146.055us 1 1 100.00
aes_config_error 2.000s 78.528us 1 1 100.00
aes_alert_reset 4.000s 781.040us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 9.000s 2447.936us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 246.115us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 781.040us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 148.530us 1 1 100.00
aes_sideload 4.000s 163.007us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 144.895us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 19.000s 1258.337us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 82.284us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 180.745us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 180.745us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 85.178us 1 1 100.00
aes_csr_rw 1.000s 55.002us 1 1 100.00
aes_csr_aliasing 2.000s 71.926us 1 1 100.00
aes_same_csr_outstanding 2.000s 129.148us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 85.178us 1 1 100.00
aes_csr_rw 1.000s 55.002us 1 1 100.00
aes_csr_aliasing 2.000s 71.926us 1 1 100.00
aes_same_csr_outstanding 2.000s 129.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 175.362us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_cipher_fi 3.000s 46.295us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 153.055us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 153.055us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 153.055us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 153.055us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 188.886us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1041.718us 1 1 100.00
aes_tl_intg_err 2.000s 176.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 176.724us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 781.040us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 153.055us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 153.055us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 85.305us 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
aes_alert_reset 4.000s 781.040us 1 1 100.00
aes_core_fi 1.000s 85.895us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 78.528us 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
aes_core_fi 1.000s 85.895us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 153.055us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 125.958us 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 148.530us 1 1 100.00
aes_sideload 4.000s 163.007us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 125.958us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 125.958us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 125.958us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 125.958us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 125.958us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 148.530us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 1089.294us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_cipher_fi 3.000s 46.295us 1 1 100.00
aes_ctr_fi 2.000s 63.090us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 1089.294us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_cipher_fi 3.000s 46.295us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 46.295us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 1089.294us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_ctr_fi 2.000s 63.090us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 1089.294us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_cipher_fi 3.000s 46.295us 1 1 100.00
aes_ctr_fi 2.000s 63.090us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 781.040us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_cipher_fi 3.000s 46.295us 1 1 100.00
aes_ctr_fi 2.000s 63.090us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_cipher_fi 3.000s 46.295us 1 1 100.00
aes_ctr_fi 2.000s 63.090us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_ctr_fi 2.000s 63.090us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 1089.294us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 1089.294us 0 1 0.00
aes_control_fi 1.000s 51.231us 1 1 100.00
aes_cipher_fi 3.000s 46.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 32.907us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 54407385455884042348039650357636094088029233856118701145276167541652023157192 5225
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 58405809292300473770310170633407901514542756292695503692776686492487539771 77897
UVM_INFO @ 1258337226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 109682722535097312582742722434892648957586104306758341133252171550425919308629 155
UVM_INFO @ 32907141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---