Simulation Results: chip

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.94 %
  • code
  • 81.34 %
  • assert
  • 97.50 %
  • func
  • 42.98 %
  • line
  • 94.28 %
  • branch
  • 93.55 %
  • cond
  • 88.56 %
  • toggle
  • 73.15 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
81.88%
V2S
100.00%
V3
65.38%
unmapped
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 178.280s 3748.394us 1 1 100.00
chip_sw_example_rom 101.040s 2601.630us 1 1 100.00
chip_sw_example_manufacturer 165.380s 3501.423us 1 1 100.00
chip_sw_example_concurrency 148.130s 2973.852us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 239.530s 6843.613us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 197.620s 4390.537us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2654.760s 33064.015us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4730.120s 32205.031us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 82.570s 2883.033us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4730.120s 32205.031us 1 1 100.00
chip_csr_rw 197.620s 4390.537us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.270s 167.074us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 323.900s 4829.983us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 323.900s 4829.983us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 323.900s 4829.983us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 340.740s 4529.385us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 340.740s 4529.385us 1 1 100.00
chip_sw_uart_tx_rx_idx1 379.570s 4779.107us 1 1 100.00
chip_sw_uart_tx_rx_idx2 366.370s 4734.251us 1 1 100.00
chip_sw_uart_tx_rx_idx3 353.860s 5029.448us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1109.060s 8855.678us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 481.030s 5015.254us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 313.280s 5517.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 293.690s 7170.731us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 293.690s 7170.731us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 272.610s 4453.396us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 277.660s 7689.367us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 216.480s 5234.031us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 107.790s 3646.884us 1 1 100.00
chip_tap_straps_testunlock0 214.330s 5098.570us 1 1 100.00
chip_tap_straps_rma 165.050s 4130.030us 1 1 100.00
chip_tap_straps_prod 625.330s 10331.059us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 455.760s 7173.475us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 455.760s 7173.475us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 559.000s 9312.795us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 775.010s 11092.141us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 424.370s 5435.106us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 574.690s 5954.073us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4126.590s 20000.995us 1 1 100.00
chip_sw_aes_enc_jitter_en 144.630s 3847.931us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 811.670s 7740.837us 1 1 100.00
chip_sw_hmac_enc_jitter_en 174.960s 3332.291us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1153.750s 11192.155us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 208.970s 4303.215us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 416.620s 5283.224us 1 1 100.00
chip_sw_clkmgr_jitter 181.490s 3784.107us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 244.380s 3316.555us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 446.960s 7318.270us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 243.340s 5999.354us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 232.600s 4210.937us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 243.340s 5999.354us 1 1 100.00
chip_sw_smoketest 16 16 100.00
chip_sw_aes_smoketest 160.860s 2955.143us 1 1 100.00
chip_sw_aon_timer_smoketest 200.340s 4226.761us 1 1 100.00
chip_sw_clkmgr_smoketest 215.410s 3702.151us 1 1 100.00
chip_sw_csrng_smoketest 192.150s 3085.158us 1 1 100.00
chip_sw_entropy_src_smoketest 802.650s 7194.392us 1 1 100.00
chip_sw_gpio_smoketest 198.980s 4062.775us 1 1 100.00
chip_sw_hmac_smoketest 250.210s 3867.776us 1 1 100.00
chip_sw_kmac_smoketest 195.180s 3814.385us 1 1 100.00
chip_sw_otbn_smoketest 1376.480s 10453.798us 1 1 100.00
chip_sw_pwrmgr_smoketest 220.140s 6114.622us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 303.850s 6316.170us 1 1 100.00
chip_sw_rv_plic_smoketest 191.470s 3728.674us 1 1 100.00
chip_sw_rv_timer_smoketest 164.970s 3417.646us 1 1 100.00
chip_sw_rstmgr_smoketest 158.190s 3387.263us 1 1 100.00
chip_sw_sram_ctrl_smoketest 176.330s 2843.226us 1 1 100.00
chip_sw_uart_smoketest 206.550s 4201.949us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 164.260s 3189.112us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 426.490s 6114.357us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 17870.340s 130742.833us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3335.600s 16954.636us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 20.150s 10.320us 0 1 0.00
chip_sw_power_idle_load 1 1 100.00
chip_sw_power_idle_load 336.770s 4759.943us 1 1 100.00
chip_sw_power_sleep_load 1 1 100.00
chip_sw_power_sleep_load 243.410s 5428.764us 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 221.420s 6566.438us 0 1 0.00
chip_sw_inject_scramble_seed 0 1 0.00
chip_sw_inject_scramble_seed 158.030s 3327.811us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 72.550s 2894.481us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 72.550s 2894.481us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4730.120s 32205.031us 1 1 100.00
chip_same_csr_outstanding 1357.130s 14782.579us 1 1 100.00
chip_csr_hw_reset 239.530s 6843.613us 1 1 100.00
chip_csr_rw 197.620s 4390.537us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4730.120s 32205.031us 1 1 100.00
chip_same_csr_outstanding 1357.130s 14782.579us 1 1 100.00
chip_csr_hw_reset 239.530s 6843.613us 1 1 100.00
chip_csr_rw 197.620s 4390.537us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 14.830s 536.518us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 3.840s 38.744us 1 1 100.00
xbar_smoke_large_delays 47.470s 7992.192us 1 1 100.00
xbar_smoke_slow_rsp 39.710s 4574.564us 1 1 100.00
xbar_random_zero_delays 24.610s 420.147us 1 1 100.00
xbar_random_large_delays 161.270s 27412.269us 1 1 100.00
xbar_random_slow_rsp 35.010s 3789.014us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 19.660s 641.581us 1 1 100.00
xbar_error_and_unmapped_addr 8.490s 102.452us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 26.700s 1196.330us 1 1 100.00
xbar_error_and_unmapped_addr 8.490s 102.452us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 24.640s 937.200us 1 1 100.00
xbar_access_same_device_slow_rsp 378.950s 44538.749us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 12.210s 197.780us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 187.420s 3458.967us 1 1 100.00
xbar_stress_all_with_error 126.140s 2575.837us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 301.670s 10554.035us 1 1 100.00
xbar_stress_all_with_reset_error 72.040s 301.189us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3335.600s 16954.636us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 19.880s 10.400us 0 1 0.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3304.040s 19061.359us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 20.690s 10.300us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 21.930s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 21.860s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 22.780s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 21.810s 10.300us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 21.140s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 21.210s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 21.290s 10.360us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 20.720s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 19.770s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 20.910s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 20.840s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 20.810s 10.140us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 21.240s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 21.030s 10.160us 0 1 0.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 2515.050s 11954.267us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 3164.480s 16942.447us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 3063.310s 15044.137us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 3080.240s 14708.306us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 3038.950s 15465.541us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2486.740s 10943.278us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3245.740s 15819.731us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 2967.180s 14894.730us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 2860.710s 14727.681us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 2980.340s 15422.592us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2490.160s 13973.516us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 2986.270s 15208.611us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3116.470s 18181.863us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3113.490s 15833.969us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 2954.450s 14535.654us 1 1 100.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 20.600s 10.380us 0 1 0.00
rom_e2e_asm_init_dev 20.040s 10.240us 0 1 0.00
rom_e2e_asm_init_prod 20.420s 10.120us 0 1 0.00
rom_e2e_asm_init_prod_end 19.700s 10.180us 0 1 0.00
rom_e2e_asm_init_rma 20.030s 10.360us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 6225.300s 28815.921us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 6146.840s 30040.995us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6212.570s 31571.916us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3120.340s 16535.324us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2654.000s 35635.137us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2654.000s 35635.137us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 175.650s 4382.867us 1 1 100.00
chip_sw_aes_enc_jitter_en 144.630s 3847.931us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 172.550s 3867.000us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 166.470s 3144.588us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1612.940s 14846.486us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 184.040s 3946.340us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 371.670s 6958.208us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 417.900s 5765.607us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 485.470s 5708.519us 1 1 100.00
chip_plic_all_irqs_10 262.330s 4732.121us 1 1 100.00
chip_plic_all_irqs_20 307.200s 4460.271us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 233.280s 3536.540us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1364.780s 14003.715us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 284.930s 4582.270us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 145.030s 2644.734us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.156s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 728.380s 7488.038us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 880.550s 7909.623us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 809.160s 8732.512us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9959.250s 255886.561us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 277.270s 5093.137us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 220.140s 6114.622us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 277.270s 5093.137us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 406.040s 8891.999us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 406.040s 8891.999us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 323.860s 7167.268us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 462.780s 8244.121us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 604.380s 6167.433us 1 1 100.00
chip_sw_aes_idle 166.470s 3144.588us 1 1 100.00
chip_sw_hmac_enc_idle 207.170s 2970.988us 1 1 100.00
chip_sw_kmac_idle 187.930s 3342.730us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 346.300s 5782.524us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 337.920s 5356.492us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 304.800s 6501.239us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 374.290s 6696.624us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 734.690s 11028.393us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 442.870s 4962.937us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 434.450s 5532.501us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 373.880s 4714.049us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 369.990s 4736.758us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 428.390s 5534.823us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 371.720s 5513.095us 1 1 100.00
chip_sw_ast_clk_outputs 559.000s 9312.795us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 376.920s 9023.416us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 373.880s 4714.049us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 369.990s 4736.758us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 424.370s 5435.106us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 574.690s 5954.073us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4126.590s 20000.995us 1 1 100.00
chip_sw_aes_enc_jitter_en 144.630s 3847.931us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 811.670s 7740.837us 1 1 100.00
chip_sw_hmac_enc_jitter_en 174.960s 3332.291us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1153.750s 11192.155us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 208.970s 4303.215us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 416.620s 5283.224us 1 1 100.00
chip_sw_clkmgr_jitter 181.490s 3784.107us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 193.900s 4172.317us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 354.550s 4541.978us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 556.790s 7423.040us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4286.330s 26058.997us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 144.050s 3553.917us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 162.520s 2771.975us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 611.610s 8096.146us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 170.690s 3853.370us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 411.030s 6656.491us 1 1 100.00
chip_sw_flash_init_reduced_freq 1328.990s 28757.484us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3133.550s 26268.159us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 559.000s 9312.795us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 379.780s 4856.350us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 318.690s 4260.909us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 417.900s 5765.607us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 728.380s 7488.038us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2183.590s 24351.745us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 396.900s 6011.423us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 0 1 0.00
chip_sw_csrng_lc_hw_debug_en_test 221.610s 4448.452us 0 1 0.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 181.560s 3887.885us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3483.000s 21212.439us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 193.100s 3117.136us 1 1 100.00
chip_sw_edn_entropy_reqs 636.370s 7448.732us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 193.100s 3117.136us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2183.590s 24351.745us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 169.890s 3934.694us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1139.380s 20438.648us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 594.290s 6844.624us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 574.690s 5954.073us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 349.750s 5477.774us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 424.370s 5435.106us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 7189.580s 94111.751us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1139.380s 20438.648us 1 1 100.00
chip_sw_flash_idle_low_power 0 1 0.00
chip_sw_flash_ctrl_idle_low_power 314.980s 7456.284us 0 1 0.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1584.560s 13945.377us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 249.810s 4246.214us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 7189.580s 94111.751us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 249.810s 4246.214us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 249.810s 4246.214us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 249.810s 4246.214us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 249.810s 4246.214us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 417.900s 5765.607us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 332.560s 12850.826us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 545.580s 5907.977us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 464.410s 6731.154us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 464.410s 6731.154us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 176.160s 3079.346us 1 1 100.00
chip_sw_hmac_enc_jitter_en 174.960s 3332.291us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 207.170s 2970.988us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 913.120s 8357.370us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1517.810s 12018.488us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 369.120s 5009.517us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 335.610s 4810.054us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 350.400s 5922.759us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 303.770s 4569.018us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1584.560s 13945.377us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1153.750s 11192.155us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1349.640s 11173.822us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1612.940s 14846.486us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 5251.780s 20026.704us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 174.050s 3682.787us 1 1 100.00
chip_sw_kmac_mode_kmac 169.480s 3759.925us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 208.970s 4303.215us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1584.560s 13945.377us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 865.460s 17731.122us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 185.820s 3569.261us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 850.360s 7920.726us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 187.930s 3342.730us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 371.670s 6958.208us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 107.790s 3646.884us 1 1 100.00
chip_tap_straps_rma 165.050s 4130.030us 1 1 100.00
chip_tap_straps_prod 625.330s 10331.059us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 167.470s 2795.490us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 865.460s 17731.122us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 865.460s 17731.122us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 865.460s 17731.122us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1255.800s 11933.147us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_sw_flash_ctrl_lc_rw_en 249.810s 4246.214us 0 1 0.00
chip_sw_flash_rma_unlocked 7189.580s 94111.751us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 262.490s 3455.209us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 484.140s 7455.927us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 494.940s 8995.983us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 470.610s 6790.953us 0 1 0.00
chip_sw_lc_ctrl_transition 865.460s 17731.122us 1 1 100.00
chip_sw_keymgr_key_derivation 1584.560s 13945.377us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 322.690s 11649.592us 1 1 100.00
chip_sw_sram_ctrl_execution_main 607.520s 12547.193us 1 1 100.00
chip_prim_tl_access 332.560s 12850.826us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 376.920s 9023.416us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 442.870s 4962.937us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 434.450s 5532.501us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 373.880s 4714.049us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 369.990s 4736.758us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 428.390s 5534.823us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 371.720s 5513.095us 1 1 100.00
chip_tap_straps_dev 107.790s 3646.884us 1 1 100.00
chip_tap_straps_rma 165.050s 4130.030us 1 1 100.00
chip_tap_straps_prod 625.330s 10331.059us 1 1 100.00
chip_rv_dm_lc_disabled 366.120s 12100.123us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 203.410s 4323.915us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 85.280s 3228.979us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 101.570s 3016.643us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 177.800s 3674.717us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_sw_lc_walkthrough_testunlocks 1786.440s 36798.742us 1 1 100.00
chip_rv_dm_lc_disabled 366.120s 12100.123us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 797.350s 15029.157us 0 1 0.00
chip_sw_lc_walkthrough_prod 842.620s 16146.666us 0 1 0.00
chip_sw_lc_walkthrough_prodend 749.940s 16125.078us 1 1 100.00
chip_sw_lc_walkthrough_rma 446.800s 8522.515us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1786.440s 36798.742us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 81.530s 3110.223us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 80.060s 2792.380us 1 1 100.00
rom_volatile_raw_unlock 20.450s 10.340us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3935.940s 18271.885us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4126.590s 20000.995us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 604.380s 6167.433us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 604.380s 6167.433us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 604.380s 6167.433us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 341.040s 4206.905us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 865.460s 17731.122us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1139.380s 20438.648us 1 1 100.00
chip_sw_otbn_mem_scramble 341.040s 4206.905us 1 1 100.00
chip_sw_keymgr_key_derivation 1584.560s 13945.377us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 404.610s 6465.114us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 207.810s 3908.269us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1139.380s 20438.648us 1 1 100.00
chip_sw_otbn_mem_scramble 341.040s 4206.905us 1 1 100.00
chip_sw_keymgr_key_derivation 1584.560s 13945.377us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 404.610s 6465.114us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 207.810s 3908.269us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 865.460s 17731.122us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 378.370s 6460.225us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 167.470s 2795.490us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 262.490s 3455.209us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 484.140s 7455.927us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 494.940s 8995.983us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 470.610s 6790.953us 0 1 0.00
chip_sw_lc_ctrl_transition 865.460s 17731.122us 1 1 100.00
chip_prim_tl_access 332.560s 12850.826us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 332.560s 12850.826us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1057.090s 9144.032us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 76.870s 2946.070us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 849.610s 26343.364us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 295.480s 8766.821us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 405.190s 8697.050us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 523.290s 7235.591us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 746.720s 24454.002us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 455.430s 9946.625us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 406.040s 8891.999us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 824.510s 12007.502us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 371.050s 5614.945us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 76.870s 2946.070us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 296.020s 5747.928us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 475.520s 10190.149us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 413.280s 9678.679us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 180.310s 3442.194us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 297.370s 6465.788us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 736.150s 8350.062us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 953.030s 15869.513us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1555.380s 26282.593us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 166.500s 3599.395us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 417.900s 5765.607us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 322.690s 11649.592us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 322.690s 11649.592us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 953.030s 15869.513us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 297.370s 6465.788us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 371.050s 5614.945us 1 1 100.00
chip_sw_pwrmgr_smoketest 220.140s 6114.622us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 300.230s 5081.773us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 346.690s 8100.530us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 335.490s 6680.431us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1364.780s 14003.715us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 160.810s 3142.643us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 417.900s 5765.607us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 880.550s 7909.623us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 502.500s 5760.492us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 467.670s 5719.731us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 204.540s 4491.145us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 207.810s 3908.269us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 346.690s 8100.530us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 346.690s 8100.530us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 199.200s 3525.857us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1006.020s 16595.244us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1123.590s 17307.579us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 300.230s 5081.773us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 225.620s 4139.096us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 380.640s 8142.954us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 165.050s 4130.030us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 366.120s 12100.123us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 485.470s 5708.519us 1 1 100.00
chip_plic_all_irqs_10 262.330s 4732.121us 1 1 100.00
chip_plic_all_irqs_20 307.200s 4460.271us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 183.490s 2820.818us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 236.260s 3713.266us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3335.600s 16954.636us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 290.390s 4558.364us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 223.660s 4195.053us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 268.830s 4021.297us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 232.090s 4617.845us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 404.610s 6465.114us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 416.620s 5283.224us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 401.550s 8985.392us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 490.500s 10159.530us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 607.520s 12547.193us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 417.900s 5765.607us 1 1 100.00
chip_sw_data_integrity_escalation 455.760s 7173.475us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 736.150s 8350.062us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1014.780s 24443.619us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 167.290s 3104.181us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 225.810s 3983.342us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 377.640s 5183.025us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1014.780s 24443.619us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1014.780s 24443.619us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2312.680s 20246.112us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2312.680s 20246.112us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 317.960s 7440.773us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2654.000s 35635.137us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 138.620s 3333.645us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 151.990s 3223.533us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 253.560s 3820.455us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 326.890s 4854.461us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 906.000s 8454.358us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5041.140s 31617.897us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1748.340s 13589.240us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 198.700s 3429.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 176.080s 3652.566us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 116.320s 3302.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10727.440s 73338.568us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1067.950s 7469.587us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 180.540s 4941.438us 0 1 0.00
rom_e2e_jtag_debug_dev 437.930s 7194.433us 0 1 0.00
rom_e2e_jtag_debug_rma 205.590s 4578.068us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 73.570s 2136.116us 0 1 0.00
rom_e2e_jtag_inject_dev 76.920s 2641.213us 0 1 0.00
rom_e2e_jtag_inject_rma 86.680s 3530.942us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 126.959s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 297.740s 4152.070us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 359.710s 3939.782us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1075.470s 7139.812us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1370.000s 9889.368us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 256.710s 2743.745us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 613.520s 6162.070us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 75.160s 1985.896us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 197.280s 3414.995us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 355.980s 7107.176us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 310.240s 5705.970us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 953.030s 15869.513us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 180.540s 4941.438us 0 1 0.00
rom_e2e_jtag_debug_dev 437.930s 7194.433us 0 1 0.00
rom_e2e_jtag_debug_rma 205.590s 4578.068us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 319.880s 5536.001us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 417.900s 5765.607us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5425.150s 38480.115us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5425.150s 38480.115us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 185.650s 3950.099us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 340.740s 4529.385us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2675.950s 19743.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 12 50.00
chip_sival_flash_info_access 191.230s 3693.152us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 20.430s 10.260us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 6.160s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 172.680s 3308.026us 1 1 100.00
chip_sw_otp_ctrl_descrambling 205.270s 3897.729us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 254.920s 5053.265us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.508s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 232.920s 3733.674us 1 1 100.00
chip_sw_flash_scrambling_smoketest 199.770s 3529.069us 1 1 100.00
ate_bootstrap_flash_erase 658.010s 10010.300us 0 1 0.00
ate_bootstrap_one_frame 10800.146s 0.000us 0 1 0.00
ate_bootstrap_disjoint 163.160s 3020.400us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[RramData]] file empty_test_slot_a_prod_key_*_sim_dv.*.scr.vmem could not be opened for r mode 15 test runs
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 999757885526047395315328854142777406059194275657275973444295220185332713581 346
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_good_dev 46484095729066569668215429440057220088176576418913573573904156310379627630009 346
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_good_prod 88136852164455261068531070770735700260020715488886243940576736441906540368398 346
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 41104302630245556408274642144398096937721160023385844085064586010598559563418 346
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_good_rma 32389097510823135825027643730040136481926468632975659290135518915063499219666 346
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 51859768295220003091412385795167008619637822200320358793179298685360140575130 370
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 112403372666145348011643809809433314288113474421719761868785790751432370443959 368
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 32239476410335131957683416897960672066770699787078966187919894765728593711469 369
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 69714203181995540381261841616524302425780441189868313433413864579717086271887 375
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 26923839502741215788294125029643046696830076271892681614600084695898279650825 375
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_test_unlocked0 55935791019375637879735030211301234297987001438602459247035280768011760450654 322
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_dev 9059008758142728496767710684350025398425077753769298378617621926378705975761 322
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_prod 27777593811748618765342228346215192112141575480758212320387093443425551842547 322
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_prod_end 85697834761130596013163533335786054372053446894755824668710262457587644376664 322
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_rma 108644025021014871662212312441790665414413033913450533388376816540980597997582 322
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 18551799341615237541490941272919082124189240562483626802734477796690906076923 348
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 80151451323002304632004373112440576658896721379177132778405358449726960443191 336
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 110694781604078380302209840130485520402242878219512298054822752150623785350621 374
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 63282602770703299301591621713178665006878511891158409002020524793007936788766 336
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 108322761601860111433628655882956912913774307365655782898697994042980151884943 325
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 60450687687123053088949659340180385780579413238843158721864338440914529015170 324
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 38758689631927432732813904518528441968650634782010676048169305408861586329360 325
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_flash_ctrl_idle_low_power 75566193346012559182132721853702029157378180663250558779676693096173990597359 323
UVM_ERROR @ 7456.284000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7456.284000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 65835361240807293049809224920757081845655758113202544026528780477723027971135 330
UVM_ERROR @ 6465.788000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6465.788000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 87248957236144437198421262566398031506556403858050246214575512270343506140206 342
UVM_ERROR @ 9946.625000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9946.625000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 112620747790384404075194515240746198270713051648526386447936460812699706499264 340
UVM_ERROR @ 8697.050500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8697.050500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 110959954226600157497436547670530334662137759531158031619801919296791689079924 334
UVM_ERROR @ 8891.999000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8891.999000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[RramData]] file empty_test_slot_b_prod_key_*_sim_dv.*.scr.vmem could not be opened for r mode 5 test runs
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 81564728086169561949587229474558206233347197296407063048694110175702039040817 372
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 63626558769042758536136225058554872005251346122687843628215876041593469575025 370
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 89336150580749886993632136117986164019530456313000874209753473229416100019889 371
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 66808791668176134170142992807044503741987573324616125570264450832043972884682 372
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 59464926293539018404427351972610069793282931150768359079337038853133922453828 372
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 66723631070799769215934740757268797985811472288194465433797788068259941036412 379
UVM_INFO @ 15029.157415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 91726205700486188878441335335186541183351554347551999576575109749917505989263 379
UVM_INFO @ 16146.665550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 55474441493285928898202149428476188078950995171753072269945379801957286233377 356
UVM_INFO @ 8522.514528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
chip_sw_alert_handler_lpg_sleep_mode_pings 30668886583871700268251664793091410764312334974087996201923165587002192141447 None
ate_bootstrap_one_frame 55449968162242734850804727658560249260680760558315135158246646278157268497663 None
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:334) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 33491479928967482513029803032606678936736446022928933674068921634447326712140 357
UVM_INFO @ 12018.488028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 99043894889425037634441389633898891116108640805404558133883984548389119350187 353
UVM_INFO @ 20026.703741 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:618) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 96833522814314850496691150474620517515367426422461564279336522180363269001819 231
TL item was: req: (cip_tl_seq_item@33223) { a_addr: 'h10568 a_data: 'h840034aa a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h1b64b d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2894.481157 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 23139688656836614093094261406434014777098656293919807080050296150619958945564 238
TL item was: req: (cip_tl_seq_item@32445) { a_addr: 'h10710 a_data: 'h8c44b95f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h4 a_user: 'h1bd6b d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2883.032786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 50922064318135810629490151462435352844753689180096674771621545337286421300966 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 113965107972828902988322871850253607718641075911488104444261348963073794210834 None
Another command (pid=542942) is running. Waiting for it to complete on the server (server_pid=280819)...
Another command (pid=476700) is running. Waiting for it to complete on the server (server_pid=280819)...
Another command (pid=494300) is running. Waiting for it to complete on the server (server_pid=280819)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[RramData]] file empty_test_slot_a_test_key_*_sim_dv.*.scr.vmem could not be opened for r mode 2 test runs
rom_volatile_raw_unlock 99513422441395488383370218546325717010332327785542584746315580984518302212116 308
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_raw_unlock 36966955901988771426664655528669942548969075153617868703673167621156229264106 315
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 42353069449124595693425481929893889579682034013602247804575415142703435036599 316
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [inject_scramble_seed_sim_dv(sw/device/tests/sim_dv/inject_scramble_seed.c:60)] CHECK-STATUS-fail: * 1 test run
chip_sw_inject_scramble_seed 54345973698981573488417896602675182285098003349603505896988131876449824887257 319
UVM_INFO @ 3327.810981 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:641) virtual_sequencer [chip_sw_exit_test_unlocked_bootstrap_vseq] Failed to open sw_image file at exit_test_unlocked_bootstrap_sim_dv.*.vmem. 1 test run
chip_sw_exit_test_unlocked_bootstrap 46517307635095217567161483153233894628758178587332327988195894903419600156815 342
UVM_INFO @ 6566.437734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 111361183639810225223674560493830994630368667433082016921928176197370535445582 342
UVM_INFO @ 4195.052720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 72662525341817457239185234130184479848476067368018132209643379048434478669445 324
UVM_INFO @ 4246.213784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 80248998403104260286736715573486723379446240681169977341489513004702356998481 357
UVM_INFO @ 6790.952970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 9487619063026902171663096639842588234952894429837198109323234941861227066385 331
UVM_ERROR @ 3414.994680 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3414.994680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 88628956722806866639233904556544398136077966449300200165510899869454860889422 297
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 40879874095313904670268686659884814711130975569013160276168648887715252183386 318
UVM_ERROR @ 2946.070292 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2946.070292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 70346865623874545196447754717846098722396870359511743263700070019776601816909 328
UVM_ERROR @ 3442.194396 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3442.194396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx])' 1 test run
chip_sw_pwrmgr_random_sleep_power_glitch_reset 110217291814294740404230830418318847645826099708418995100409670549883795473285 343
UVM_ERROR @ 10190.149000 us: (pwrmgr_rstreqs_sva_if.sv:79) [ASSERT FAILED] MainPwrRstOff_A
UVM_INFO @ 10190.149000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:334) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 71322766995453905682872423767198131372642528906843136934391346271638775967872 347
UVM_INFO @ 35635.137011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:351)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 73738641974993149866211908393716914743873078989655878787522583430635184049720 322
UVM_INFO @ 3946.340348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 12059915218307052086739346133180366869135616116917347077256532427843522729867 323
UVM_INFO @ 2644.733976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== 1 test run
chip_sw_csrng_lc_hw_debug_en_test 38141373374448977232102277847781737859859425457896546045693879708587809719451 339
UVM_INFO @ 4448.451960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 44690263351799834297794925390023998014347943707591315241450878410849017930443 358
UVM_INFO @ 4152.069887 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 53976230632660637928637679000719263922946726102647682236370874849808446358356 342
UVM_INFO @ 11092.140957 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 44408258215195890871752350934980031690834889611131504125370170973247763333830 290
UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:641) virtual_sequencer [chip_sw_ate_bootstrap_disjoint_vseq] Failed to open sw_image file at multislot_empty_test_sim_dv.*.vmem. 1 test run
ate_bootstrap_disjoint 80089651528636439119187654319488638061517618975489474109515274037543569121223 318
UVM_INFO @ 3020.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[RramData]] file empty_test_slot_a_unsigned_sim_dv.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_shutdown_output 15276596322194325094967983425748844132949680555263363024544401247959266405401 327
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 65909430029836952886721397902448575134742165020485369030101028474647983533959 342
UVM_ERROR @ 6114.356666 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6114.356666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---