Simulation Results: clkmgr

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.06 %
  • code
  • 98.29 %
  • assert
  • 95.48 %
  • func
  • 85.42 %
  • line
  • 98.97 %
  • branch
  • 98.59 %
  • cond
  • 94.69 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.830s 26.051us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.780s 27.367us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.890s 26.322us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.300s 289.818us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.670s 235.418us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.040s 84.511us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.890s 26.322us 1 1 100.00
clkmgr_csr_aliasing 1.670s 235.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.700s 41.857us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.120s 108.081us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.910s 56.060us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.790s 29.972us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.830s 26.051us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 9.190s 2115.257us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 9.910s 2416.046us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 9.190s 2115.257us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 17.630s 7352.154us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.860s 43.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.260s 28.689us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.260s 28.689us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 27.367us 1 1 100.00
clkmgr_csr_rw 0.890s 26.322us 1 1 100.00
clkmgr_csr_aliasing 1.670s 235.418us 1 1 100.00
clkmgr_same_csr_outstanding 0.830s 30.803us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 27.367us 1 1 100.00
clkmgr_csr_rw 0.890s 26.322us 1 1 100.00
clkmgr_csr_aliasing 1.670s 235.418us 1 1 100.00
clkmgr_same_csr_outstanding 0.830s 30.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.810s 2.045us 0 1 0.00
clkmgr_tl_intg_err 28.450s 10042.830us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.120s 436.762us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.120s 436.762us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.120s 436.762us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.120s 436.762us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 5.780s 2223.477us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 28.450s 10042.830us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 9.190s 2115.257us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 9.910s 2416.046us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.120s 436.762us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.790s 30.039us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.870s 12.971us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.960s 106.797us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.780s 33.497us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.820s 44.948us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.890s 26.322us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.810s 2.045us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 26.322us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 26.322us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.810s 2.045us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.460s 195.981us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 48.700s 11976.908us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.measure_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 22757424420025236507242254721007493237020541017424749428221309241315225785729 82
UVM_INFO @ 2223476556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 113461607587365772136475112900606188553521750519709076877864884567082075236179 84
UVM_INFO @ 2045199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 45514617044132915941270089564819940456430199171081115921048887845143404174922 122
UVM_INFO @ 10042829794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---