Simulation Results: csrng

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.27 %
  • code
  • 92.27 %
  • assert
  • 94.32 %
  • func
  • 72.22 %
  • block
  • 96.92 %
  • line
  • 97.69 %
  • branch
  • 92.43 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 52.589us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 28.251us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 40.356us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 20.000s 676.231us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 6.000s 295.818us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 35.140us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 40.356us 1 1 100.00
csrng_csr_aliasing 6.000s 295.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
alerts 1 1 100.00
csrng_alert 11.000s 732.544us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 50.000s 4980.914us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 50.000s 4980.914us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 31.000s 666.238us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 16.767us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 58.537us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 119.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 119.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 28.251us 1 1 100.00
csrng_csr_rw 2.000s 40.356us 1 1 100.00
csrng_csr_aliasing 6.000s 295.818us 1 1 100.00
csrng_same_csr_outstanding 3.000s 167.642us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 28.251us 1 1 100.00
csrng_csr_rw 2.000s 40.356us 1 1 100.00
csrng_csr_aliasing 6.000s 295.818us 1 1 100.00
csrng_same_csr_outstanding 3.000s 167.642us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 162.276us 1 1 100.00
csrng_tl_intg_err 8.000s 158.321us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 5.811us 0 1 0.00
csrng_csr_rw 2.000s 40.356us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 11.000s 732.544us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 31.000s 666.238us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
csrng_sec_cm 3.000s 162.276us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
csrng_sec_cm 3.000s 162.276us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
csrng_sec_cm 3.000s 162.276us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
csrng_sec_cm 3.000s 162.276us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
csrng_sec_cm 3.000s 162.276us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 11.000s 732.544us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 31.000s 666.238us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 11.000s 732.544us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 8.000s 158.321us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
csrng_sec_cm 3.000s 162.276us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
csrng_sec_cm 3.000s 162.276us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 99.015us 1 1 100.00
csrng_err 3.000s 33.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 35.000s 948.881us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 38757446764268266290371304091374341845654026675784014856408684497117398983599 99
UVM_INFO @ 5811149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 37909529966742831047646108656818100807220431420266903711640351645762378784962 153
UVM_INFO @ 948881065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---