Simulation Results: edn/edn0

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.90 %
  • code
  • 80.19 %
  • assert
  • 96.75 %
  • func
  • 80.75 %
  • line
  • 97.34 %
  • branch
  • 90.93 %
  • cond
  • 86.65 %
  • toggle
  • 77.64 %
  • FSM
  • 48.39 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 47.153us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.890s 17.342us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.820s 13.057us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.740s 544.805us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 29.878us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 26.993us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.820s 13.057us 1 1 100.00
edn_csr_aliasing 1.120s 29.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.530s 47.899us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.530s 47.899us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.530s 47.899us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.950s 34.851us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 95.710us 1 1 100.00
errs 1 1 100.00
edn_err 1.090s 28.002us 1 1 100.00
disable 1 2 50.00
edn_disable 0.780s 43.176us 1 1 100.00
edn_disable_auto_req_mode 1.120s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.330s 240.586us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.900s 17.873us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.010s 16.714us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.070s 311.691us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.070s 311.691us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.890s 17.342us 1 1 100.00
edn_csr_rw 0.820s 13.057us 1 1 100.00
edn_csr_aliasing 1.120s 29.878us 1 1 100.00
edn_same_csr_outstanding 1.200s 118.786us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.890s 17.342us 1 1 100.00
edn_csr_rw 0.820s 13.057us 1 1 100.00
edn_csr_aliasing 1.120s 29.878us 1 1 100.00
edn_same_csr_outstanding 1.200s 118.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.280s 481.990us 1 1 100.00
edn_tl_intg_err 1.970s 924.879us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 56.727us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 95.710us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.280s 481.990us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.280s 481.990us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.280s 481.990us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.280s 481.990us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 95.710us 1 1 100.00
edn_sec_cm 3.280s 481.990us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 95.710us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.970s 924.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 76.720s 4919.834us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 15999936861869509880590978840347840755133449571742596671118580921498465384450 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---