Simulation Results: edn/edn1

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.85 %
  • code
  • 82.44 %
  • assert
  • 97.66 %
  • func
  • 80.46 %
  • line
  • 98.03 %
  • branch
  • 93.07 %
  • cond
  • 89.77 %
  • toggle
  • 85.88 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 20.312us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 16.511us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.820s 21.447us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.710s 668.575us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 66.892us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.840s 18.901us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.820s 21.447us 1 1 100.00
edn_csr_aliasing 1.030s 66.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.940s 56.858us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.940s 56.858us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.940s 56.858us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 27.527us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 26.195us 1 1 100.00
errs 1 1 100.00
edn_err 0.820s 76.930us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 14.346us 1 1 100.00
edn_disable_auto_req_mode 1.150s 54.143us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.990s 603.101us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 30.364us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 30.976us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.420s 98.505us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.420s 98.505us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 16.511us 1 1 100.00
edn_csr_rw 0.820s 21.447us 1 1 100.00
edn_csr_aliasing 1.030s 66.892us 1 1 100.00
edn_same_csr_outstanding 0.820s 24.491us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 16.511us 1 1 100.00
edn_csr_rw 0.820s 21.447us 1 1 100.00
edn_csr_aliasing 1.030s 66.892us 1 1 100.00
edn_same_csr_outstanding 0.820s 24.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.970s 282.068us 1 1 100.00
edn_tl_intg_err 1.630s 274.940us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 31.561us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 26.195us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.970s 282.068us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.970s 282.068us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.970s 282.068us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.970s 282.068us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 26.195us 1 1 100.00
edn_sec_cm 2.970s 282.068us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 26.195us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.630s 274.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 45.840s 6579.691us 1 1 100.00