Simulation Results: entropy_src/rng_4bits

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.95 %
  • code
  • 88.45 %
  • assert
  • 84.24 %
  • func
  • 55.17 %
  • block
  • 94.51 %
  • line
  • 97.19 %
  • branch
  • 86.75 %
  • toggle
  • 76.12 %
  • FSM
  • 93.75 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 77.619us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 29.510us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 3.000s 68.895us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 11.000s 975.763us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 499.506us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 5.463us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 3.000s 68.895us 1 1 100.00
entropy_src_csr_aliasing 3.000s 499.506us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 77.619us 1 1 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
entropy_src_fw_ov 104.000s 13059.195us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 104.000s 13059.195us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 89.000s 14058.883us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
entropy_src_intr 9.000s 2003.616us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
entropy_src_functional_alerts 5.000s 772.719us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 184.000s 14272.157us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 160.255us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 62.673us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 16.113us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 46.533us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 218.105us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 218.105us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 29.510us 1 1 100.00
entropy_src_csr_rw 3.000s 68.895us 1 1 100.00
entropy_src_csr_aliasing 3.000s 499.506us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 78.802us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 29.510us 1 1 100.00
entropy_src_csr_rw 3.000s 68.895us 1 1 100.00
entropy_src_csr_aliasing 3.000s 499.506us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 78.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 56.521us 1 1 100.00
entropy_src_tl_intg_err 3.000s 118.187us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
entropy_src_cfg_regwen 2.000s 27.948us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
entropy_src_fw_ov 104.000s 13059.195us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 160.255us 1 1 100.00
entropy_src_sec_cm 3.000s 56.521us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 160.255us 1 1 100.00
entropy_src_sec_cm 3.000s 56.521us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 51.000s 13112.323us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 160.255us 1 1 100.00
entropy_src_sec_cm 3.000s 56.521us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 160.255us 1 1 100.00
entropy_src_sec_cm 3.000s 56.521us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 160.255us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 772.719us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 118.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 52.000s 13190.162us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 13.000s 1681.617us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 90150935466703237712284032883581399199954353958719448147612767022112300305348 129
UVM_INFO @ 1681616605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 85049822034861835236736295264352310160203025377842354409819524004357343459905 113
UVM_INFO @ 5462599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---