Simulation Results: flash_ctrl

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.62 %
  • code
  • 93.78 %
  • assert
  • 96.94 %
  • func
  • 96.13 %
  • line
  • 95.97 %
  • branch
  • 97.12 %
  • cond
  • 93.85 %
  • toggle
  • 95.55 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 81.490s 216.899us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.260s 123.168us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.740s 101.082us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.150s 39.069us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 58.650s 7399.724us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 38.630s 2834.932us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 10.890s 50.046us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.150s 39.069us 1 1 100.00
flash_ctrl_csr_aliasing 38.630s 2834.932us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.770s 16.961us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.760s 19.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.720s 24.866us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 32.990s 54.392us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1044.490s 271876.881us 1 1 100.00
flash_ctrl_hw_rma_reset 498.110s 40132.640us 1 1 100.00
flash_ctrl_lcmgr_intg 6.020s 65.135us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1396.570s 291876.916us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 156.880s 2868.008us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.920s 22.276us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1646.080s 436155.286us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 57.130s 8541.501us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.390s 34.922us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.600s 31.345us 1 1 100.00
flash_ctrl_re_evict 16.550s 140.069us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 77.250s 72.183us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 77.250s 72.183us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 229.890s 65122.208us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.940s 158.027us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 195.900s 608.591us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 354.360s 12427.632us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 331.830s 396.631us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1082.990s 6312.394us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.290s 24.324us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 128.290s 7120.662us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 15.730s 18.207us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.920s 71.943us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 332.270s 133.275us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 48.840s 1269.167us 1 1 100.00
flash_ctrl_otp_reset 42.840s 81.579us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1044.490s 271876.881us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 141.800s 6736.252us 1 1 100.00
flash_ctrl_intr_wr 44.490s 3673.277us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 153.650s 12033.857us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 169.860s 416035.056us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 39.570s 5716.649us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 33.880s 1066.926us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.480s 54.788us 1 1 100.00
flash_ctrl_ro_derr 82.890s 1870.032us 1 1 100.00
flash_ctrl_rw_derr 136.850s 3173.551us 1 1 100.00
flash_ctrl_derr_detect 111.440s 4729.443us 1 1 100.00
flash_ctrl_integrity 335.570s 4317.732us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.400s 30.605us 1 1 100.00
flash_ctrl_ro_serr 69.860s 687.722us 1 1 100.00
flash_ctrl_rw_serr 144.450s 6363.779us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 33.340s 5056.672us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 39.450s 751.646us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 1123.890s 200000.000us 0 1 0.00
flash_ctrl_write_word_sweep 6.720s 162.649us 1 1 100.00
flash_ctrl_read_word_sweep 6.090s 116.620us 1 1 100.00
flash_ctrl_ro 58.110s 1176.186us 1 1 100.00
flash_ctrl_rw 336.380s 10072.030us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.560s 1115.964us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 546.510s 157798.301us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 32.880s 10042.164us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.280s 48.810us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.110s 19.251us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.640s 108.461us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.640s 108.461us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.740s 101.082us 1 1 100.00
flash_ctrl_csr_rw 8.150s 39.069us 1 1 100.00
flash_ctrl_csr_aliasing 38.630s 2834.932us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.060s 119.105us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.740s 101.082us 1 1 100.00
flash_ctrl_csr_rw 8.150s 39.069us 1 1 100.00
flash_ctrl_csr_aliasing 38.630s 2834.932us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.060s 119.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.250s 111.671us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 26.250s 111.671us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.250s 111.671us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 26.250s 111.671us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 33.730s 531.735us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1675.160s 3568.721us 1 1 100.00
flash_ctrl_tl_intg_err 194.870s 583.305us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 194.870s 583.305us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 194.870s 583.305us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.930s 250.502us 1 1 100.00
flash_ctrl_wr_intg 6.690s 878.298us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 81.490s 216.899us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 42.840s 81.579us 1 1 100.00
flash_ctrl_disable 15.730s 18.207us 1 1 100.00
flash_ctrl_sec_info_access 40.600s 5297.376us 1 1 100.00
flash_ctrl_connect 7.920s 71.943us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.950s 120.115us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.150s 39.069us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.250s 111.671us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.150s 39.069us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.250s 111.671us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.150s 39.069us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.250s 111.671us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 15.730s 18.207us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.930s 250.502us 1 1 100.00
flash_ctrl_access_after_disable 6.140s 81.129us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.470s 67.714us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 15.730s 18.207us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.940s 158.027us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 336.380s 10072.030us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 144.450s 6363.779us 1 1 100.00
flash_ctrl_rw_derr 136.850s 3173.551us 1 1 100.00
flash_ctrl_integrity 335.570s 4317.732us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1044.490s 271876.881us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1675.160s 3568.721us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1675.160s 3568.721us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1675.160s 3568.721us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1675.160s 3568.721us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 7.700s 838.708us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.260s 39.655us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.340s 330.960us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1675.160s 3568.721us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1675.160s 3568.721us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1675.160s 3568.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.980s 313.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 426.820s 6416.781us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_wo 90259343891892367077076016493068396371608292015021832837375239224506463791445 119
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---