Simulation Results: hmac

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.97 %
  • code
  • 97.76 %
  • assert
  • 97.38 %
  • func
  • 44.77 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.760s 920.764us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.830s 258.434us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.710s 38.770us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.180s 3018.887us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.500s 104.615us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 542.850s 293714.978us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.710s 38.770us 1 1 100.00
hmac_csr_aliasing 3.500s 104.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 51.280s 6251.176us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 9.770s 304.899us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.970s 515.839us 1 1 100.00
hmac_test_sha384_vectors 19.150s 518.072us 1 1 100.00
hmac_test_sha512_vectors 350.170s 31954.929us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 1065.830us 1 1 100.00
hmac_test_hmac384_vectors 6.420s 1281.510us 1 1 100.00
hmac_test_hmac512_vectors 7.670s 1223.173us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.550s 1054.986us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 690.540s 49143.311us 1 1 100.00
error 1 1 100.00
hmac_error 80.940s 12343.787us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 71.350s 5756.821us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.760s 920.764us 1 1 100.00
hmac_long_msg 51.280s 6251.176us 1 1 100.00
hmac_back_pressure 9.770s 304.899us 1 1 100.00
hmac_datapath_stress 690.540s 49143.311us 1 1 100.00
hmac_burst_wr 8.550s 1054.986us 1 1 100.00
hmac_stress_all 185.930s 79031.523us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.760s 920.764us 1 1 100.00
hmac_long_msg 51.280s 6251.176us 1 1 100.00
hmac_back_pressure 9.770s 304.899us 1 1 100.00
hmac_datapath_stress 690.540s 49143.311us 1 1 100.00
hmac_wipe_secret 71.350s 5756.821us 1 1 100.00
hmac_test_sha256_vectors 7.970s 515.839us 1 1 100.00
hmac_test_sha384_vectors 19.150s 518.072us 1 1 100.00
hmac_test_sha512_vectors 350.170s 31954.929us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 1065.830us 1 1 100.00
hmac_test_hmac384_vectors 6.420s 1281.510us 1 1 100.00
hmac_test_hmac512_vectors 7.670s 1223.173us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.760s 920.764us 1 1 100.00
hmac_long_msg 51.280s 6251.176us 1 1 100.00
hmac_back_pressure 9.770s 304.899us 1 1 100.00
hmac_datapath_stress 690.540s 49143.311us 1 1 100.00
hmac_burst_wr 8.550s 1054.986us 1 1 100.00
hmac_error 80.940s 12343.787us 1 1 100.00
hmac_wipe_secret 71.350s 5756.821us 1 1 100.00
hmac_test_sha256_vectors 7.970s 515.839us 1 1 100.00
hmac_test_sha384_vectors 19.150s 518.072us 1 1 100.00
hmac_test_sha512_vectors 350.170s 31954.929us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 1065.830us 1 1 100.00
hmac_test_hmac384_vectors 6.420s 1281.510us 1 1 100.00
hmac_test_hmac512_vectors 7.670s 1223.173us 1 1 100.00
hmac_stress_all 185.930s 79031.523us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 185.930s 79031.523us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.620s 27.231us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 32.091us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.170s 358.057us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.170s 358.057us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.830s 258.434us 1 1 100.00
hmac_csr_rw 0.710s 38.770us 1 1 100.00
hmac_csr_aliasing 3.500s 104.615us 1 1 100.00
hmac_same_csr_outstanding 1.520s 46.208us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.830s 258.434us 1 1 100.00
hmac_csr_rw 0.710s 38.770us 1 1 100.00
hmac_csr_aliasing 3.500s 104.615us 1 1 100.00
hmac_same_csr_outstanding 1.520s 46.208us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.720s 163.993us 1 1 100.00
hmac_tl_intg_err 1.500s 188.494us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.500s 188.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.760s 920.764us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.670s 763.288us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 177.440s 11409.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.950s 599.761us 1 1 100.00