Simulation Results

Simulation Results: i2c

13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.01 %

code
78.24 %

assert
96.19 %

func
77.59 %

line
96.41 %

branch
92.26 %

cond
84.78 %

toggle
73.69 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	30.420s	7724.828us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	5.350s	670.608us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.690s	31.961us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.650s	17.498us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.650s	4323.400us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.400s	113.337us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.750s	31.083us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.650s	17.498us	1	1	100.00
	i2c_csr_aliasing	1.400s	113.337us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.620s	90.263us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	2.760s	403.968us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	17.330s	7686.751us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.650s	74.952us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	159.330s	68924.999us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	32.680s	2367.365us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.840s	120.706us	1	1	100.00
	i2c_host_fifo_fmt_empty	11.830s	1922.801us	1	1	100.00
	i2c_host_fifo_reset_rx	3.590s	900.106us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	40.140s	23401.163us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	9.350s	1733.658us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.670s	57.415us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.670s	1508.666us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	40.970s	26289.136us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.280s	939.910us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	36.490s	13377.181us	1	1	100.00
	i2c_target_intr_smoke	4.650s	2521.740us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.790s	396.070us	1	1	100.00
	i2c_target_fifo_reset_tx	0.710s	130.302us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	67.520s	46391.470us	1	1	100.00
	i2c_target_stress_rd	36.490s	13377.181us	1	1	100.00
	i2c_target_intr_stress_wr	9.210s	13592.767us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.190s	5530.400us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	4.190s	3334.389us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.780s	4824.674us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	19.550s	10134.935us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.140s	265.288us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.810s	194.763us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	17.330s	7686.751us	1	1	100.00
	i2c_host_perf_precise	1.110s	169.002us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	9.350s	1733.658us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.910s	133.932us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.680s	569.866us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.610s	519.966us	1	1	100.00
	i2c_target_nack_txstretch	1.190s	693.528us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	2.040s	938.613us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.350s	2318.567us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.620s	36.596us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.620s	21.235us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.340s	34.396us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.340s	34.396us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.690s	31.961us	1	1	100.00
	i2c_csr_rw	0.650s	17.498us	1	1	100.00
	i2c_csr_aliasing	1.400s	113.337us	1	1	100.00
	i2c_same_csr_outstanding	0.840s	26.432us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.690s	31.961us	1	1	100.00
	i2c_csr_rw	0.650s	17.498us	1	1	100.00
	i2c_csr_aliasing	1.400s	113.337us	1	1	100.00
	i2c_same_csr_outstanding	0.840s	26.432us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.090s	202.854us	1	1	100.00
	i2c_sec_cm	0.830s	241.957us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.090s	202.854us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	3.360s	425.582us	1
target_error_intr				1
	i2c_target_unexp_stop	1.180s	141.137us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	19.940s	957.037us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	74852859964391153266835179806393013970327691448646706043287121752930023953417	91	UVM_INFO @ 90263370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	93639531260870443241646968349501790697798614644117722801285485470808343399191	145	UVM_INFO @ 403967581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	19111457934676975088570297956504126518141469958947370251239587512817617049332	92	UVM_INFO @ 57414761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	84956498689167202239862162719251528826472030440640041583161701761910525769709	95	UVM_INFO @ 425582443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	80386909708300766532830154279292050759814603840323475600393981316290821589170	105	UVM_INFO @ 957036550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	79678669622271850489784144393150384054052520901316855166449225416683152204105	95	UVM_INFO @ 1508666122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'				1 test run
	i2c_target_unexp_stop	95794118389567379926675732602091767972859490088692367371271359634966163452979	90	UVM_ERROR @ 141137289 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 141137289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	26642776846072135343761087733607322169804801432782151950625283837999594493764	90	UVM_INFO @ 10134934551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---