Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.68 %
  • code
  • 83.42 %
  • assert
  • 93.85 %
  • func
  • 91.76 %
  • line
  • 97.11 %
  • branch
  • 93.27 %
  • cond
  • 79.22 %
  • toggle
  • 87.71 %
  • FSM
  • 59.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.890s 83.398us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.750s 123.761us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.760s 22.287us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.980s 45.874us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 33.865us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.850s 55.093us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.760s 22.287us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 33.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.130s 107.118us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.880s 285.286us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 14.322us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.450s 85.199us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.030s 686.434us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_prog_failure 1.450s 85.199us 1 1 100.00
lc_ctrl_errors 4.030s 686.434us 1 1 100.00
lc_ctrl_security_escalation 3.480s 1034.525us 1 1 100.00
lc_ctrl_jtag_state_failure 13.800s 7865.204us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.650s 385.403us 1 1 100.00
lc_ctrl_jtag_errors 10.810s 1079.895us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.090s 647.741us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.840s 1109.715us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.650s 385.403us 1 1 100.00
lc_ctrl_jtag_errors 10.810s 1079.895us 1 1 100.00
lc_ctrl_jtag_access 1.660s 535.460us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.470s 4212.089us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.170s 227.053us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.170s 785.906us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.280s 930.109us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.130s 859.770us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.990s 74.170us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.200s 108.513us 1 1 100.00
lc_ctrl_jtag_alert_test 0.840s 21.760us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.460s 585.838us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.740s 14.631us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 64.860s 7516.631us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.750s 26.511us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.650s 154.899us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.650s 154.899us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 123.761us 1 1 100.00
lc_ctrl_csr_rw 0.760s 22.287us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 33.865us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 30.070us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 123.761us 1 1 100.00
lc_ctrl_csr_rw 0.760s 22.287us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 33.865us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 30.070us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
lc_ctrl_tl_intg_err 1.500s 306.549us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.500s 306.549us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.880s 285.286us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.040s 273.961us 1 1 100.00
lc_ctrl_sec_cm 5.600s 2011.689us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.480s 1034.525us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.130s 107.118us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.840s 1109.715us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.230s 450.383us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.230s 450.383us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.270s 538.159us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.840s 2210.987us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.840s 2210.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 11.060s 5748.747us 1 1 100.00