Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.67 %
  • code
  • 83.62 %
  • assert
  • 94.83 %
  • func
  • 93.55 %
  • line
  • 97.00 %
  • branch
  • 93.23 %
  • cond
  • 79.20 %
  • toggle
  • 85.14 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.190s 497.209us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.780s 18.757us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.790s 18.541us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.230s 132.516us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 15.853us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 21.591us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.790s 18.541us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 15.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.560s 80.171us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.180s 345.828us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 13.017us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.720s 61.222us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.710s 1249.080us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_prog_failure 1.720s 61.222us 1 1 100.00
lc_ctrl_errors 4.710s 1249.080us 1 1 100.00
lc_ctrl_security_escalation 4.510s 685.043us 1 1 100.00
lc_ctrl_jtag_state_failure 13.010s 3936.049us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.530s 1042.218us 1 1 100.00
lc_ctrl_jtag_errors 18.890s 2155.721us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.490s 1247.034us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.480s 2029.839us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.530s 1042.218us 1 1 100.00
lc_ctrl_jtag_errors 18.890s 2155.721us 1 1 100.00
lc_ctrl_jtag_access 6.000s 14786.849us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 5.240s 601.834us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 0.920s 87.796us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.270s 254.539us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.540s 671.636us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.440s 10093.569us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.860s 17.517us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.450s 85.447us 1 1 100.00
lc_ctrl_jtag_alert_test 0.890s 38.976us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.470s 3665.895us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.030s 41.538us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 7.280s 395.425us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.920s 83.403us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.510s 132.244us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.510s 132.244us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 18.757us 1 1 100.00
lc_ctrl_csr_rw 0.790s 18.541us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 15.853us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.890s 29.697us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 18.757us 1 1 100.00
lc_ctrl_csr_rw 0.790s 18.541us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 15.853us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.890s 29.697us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
lc_ctrl_tl_intg_err 1.730s 235.636us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.730s 235.636us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.180s 345.828us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.570s 438.492us 1 1 100.00
lc_ctrl_sec_cm 5.890s 2602.264us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.510s 685.043us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.560s 80.171us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.480s 2029.839us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.370s 1420.829us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.370s 1420.829us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.540s 207.046us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.230s 1473.367us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.230s 1473.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 18.740s 1784.770us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 36789915103033583041230811908190075950749602149729725808733724927637296201072 649
UVM_INFO @ 1784770058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---