Simulation Results: otp_ctrl

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.01 %
  • code
  • 77.09 %
  • assert
  • 94.76 %
  • func
  • 71.17 %
  • line
  • 88.55 %
  • branch
  • 83.45 %
  • cond
  • 90.35 %
  • toggle
  • 79.01 %
  • FSM
  • 44.10 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.240s 109.676us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.140s 791.698us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.850s 1571.500us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.240s 110.774us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.440s 419.118us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.380s 79.827us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.630s 194.245us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.240s 110.774us 1 1 100.00
otp_ctrl_csr_aliasing 3.380s 79.827us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.060s 144.879us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.190s 554.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.240s 6025.492us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.970s 210.542us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 7.890s 621.245us 1 1 100.00
otp_ctrl_check_fail 5.810s 1462.793us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.770s 2952.988us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 4.970s 248.865us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 8.040s 2030.850us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 15.100s 3801.190us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.110s 694.918us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 12.740s 1729.231us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 27.830s 5998.301us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 4.020s 456.876us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.170s 53.916us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.680s 261.425us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.610s 1789.384us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.610s 1789.384us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.850s 1571.500us 1 1 100.00
otp_ctrl_csr_rw 1.240s 110.774us 1 1 100.00
otp_ctrl_csr_aliasing 3.380s 79.827us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.800s 115.995us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.850s 1571.500us 1 1 100.00
otp_ctrl_csr_rw 1.240s 110.774us 1 1 100.00
otp_ctrl_csr_aliasing 3.380s 79.827us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.800s 115.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
otp_ctrl_tl_intg_err 6.360s 1299.332us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.360s 1299.332us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.140s 791.698us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.140s 791.698us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
otp_ctrl_macro_errs 12.740s 1729.231us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
otp_ctrl_macro_errs 12.740s 1729.231us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.450s 512.148us 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.970s 210.542us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.810s 1462.793us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 4.970s 248.865us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 4.970s 248.865us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 4.970s 248.865us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 4.970s 248.865us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 4.970s 248.865us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.140s 791.698us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 4.970s 248.865us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.140s 791.698us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.460s 25484.594us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.770s 2952.988us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.140s 791.698us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.140s 791.698us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 12.740s 1729.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.040s 8760.617us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 54.530s 5739.815us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 108766080811422068703409464832020816227461578240139614815747091921086568817991 3199
UVM_INFO @ 1462793361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 16154332061119538104654224152454565915592250264610591359838683959177338369081 21615
UVM_INFO @ 5739815220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---