Simulation Results: pwrmgr

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.44 %
  • code
  • 97.40 %
  • assert
  • 97.39 %
  • func
  • 97.53 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.90 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.590s 31.896us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.610s 77.218us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.590s 36.577us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.380s 107.655us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.730s 94.964us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.740s 110.561us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.590s 36.577us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 94.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.790s 234.868us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.790s 234.868us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.660s 80.538us 1 1 100.00
pwrmgr_lowpower_invalid 0.620s 118.031us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.280s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.710s 166.499us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.280s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.770s 523.557us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.860s 276.563us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.620s 83.988us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.760s 1792.056us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.580s 48.906us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 0.970s 178.238us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 0.970s 178.238us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.610s 77.218us 1 1 100.00
pwrmgr_csr_rw 0.590s 36.577us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 94.964us 1 1 100.00
pwrmgr_same_csr_outstanding 0.680s 60.893us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.610s 77.218us 1 1 100.00
pwrmgr_csr_rw 0.590s 36.577us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 94.964us 1 1 100.00
pwrmgr_same_csr_outstanding 0.680s 60.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.920s 101.426us 1 1 100.00
pwrmgr_sec_cm 1.500s 754.687us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.500s 754.687us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.500s 754.687us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.920s 101.426us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.650s 971.325us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.770s 523.557us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.670s 978.768us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.770s 69.859us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.570s 31.542us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.500s 754.687us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.500s 754.687us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.500s 754.687us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 64.304us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.580s 22.272us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.830s 307.705us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 36.577us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 36.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.720s 251.200us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.650s 7961.774us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 77392639120190394897151868549407656708904524282153050823435406553154936381935 185
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 70190183908140618037222072182574080535404982191161639140273960701616935519976 90
UVM_ERROR @ 251200402 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 251200402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---