Simulation Results: rom_ctrl/64kb

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.99 %
  • code
  • 88.00 %
  • assert
  • 97.10 %
  • func
  • 96.87 %
  • line
  • 97.88 %
  • branch
  • 98.54 %
  • cond
  • 95.69 %
  • toggle
  • 94.56 %
  • FSM
  • 53.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.460s 375.787us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.310s 51.818us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.180s 53.659us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.020s 170.600us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.020s 57.840us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.260s 105.087us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.180s 53.659us 1 1 100.00
rom_ctrl_csr_aliasing 3.020s 57.840us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.060s 50.224us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.860s 78.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.990s 342.002us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 21.030s 1443.012us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 4.970s 63.095us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.990s 58.908us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.390s 60.903us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.390s 60.903us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.310s 51.818us 1 1 100.00
rom_ctrl_csr_rw 3.180s 53.659us 1 1 100.00
rom_ctrl_csr_aliasing 3.020s 57.840us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.930s 101.286us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.310s 51.818us 1 1 100.00
rom_ctrl_csr_rw 3.180s 53.659us 1 1 100.00
rom_ctrl_csr_aliasing 3.020s 57.840us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.930s 101.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.410s 252.482us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 440.620s 2301.082us 1 1 100.00
rom_ctrl_tl_intg_err 89.560s 1061.540us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 440.620s 2301.082us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 440.620s 2301.082us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 440.620s 2301.082us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 440.620s 2301.082us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.460s 375.787us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.460s 375.787us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.460s 375.787us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 89.560s 1061.540us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 4.970s 63.095us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.103s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.410s 252.482us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 440.620s 2301.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 27.880s 3068.514us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 45244335877230573546391129195321779720937160612513315166970297296730968183860 90
UVM_INFO @ 342001537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 35779925051217403276032944996388720253728781472858799504354360752645258894370 None