Simulation Results: rstmgr

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.11 %
  • code
  • 99.41 %
  • assert
  • 98.66 %
  • func
  • 96.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.230s 293.191us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.740s 98.201us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.660s 61.658us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 6.980s 2469.541us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.360s 230.370us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.820s 121.911us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.660s 61.658us 1 1 100.00
rstmgr_csr_aliasing 1.360s 230.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.730s 174.784us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.210s 147.573us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.110s 257.582us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.240s 856.367us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.240s 856.367us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.240s 856.367us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.240s 856.367us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 21.680s 8694.564us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.700s 66.329us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.080s 445.789us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.080s 445.789us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.740s 98.201us 1 1 100.00
rstmgr_csr_rw 0.660s 61.658us 1 1 100.00
rstmgr_csr_aliasing 1.360s 230.370us 1 1 100.00
rstmgr_same_csr_outstanding 0.950s 152.413us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.740s 98.201us 1 1 100.00
rstmgr_csr_rw 0.660s 61.658us 1 1 100.00
rstmgr_csr_aliasing 1.360s 230.370us 1 1 100.00
rstmgr_same_csr_outstanding 0.950s 152.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 17.490s 17048.760us 1 1 100.00
rstmgr_tl_intg_err 2.340s 940.584us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 17.490s 17048.760us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 17.490s 17048.760us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.340s 940.584us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.900s 117.622us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.410s 2824.302us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.980s 302.085us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 17.490s 17048.760us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.660s 61.658us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.660s 61.658us 1 1 100.00