Simulation Results: rv_timer

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.11 %
  • code
  • 94.66 %
  • assert
  • 98.41 %
  • func
  • 98.24 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.610s 141.017us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 70.143us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 20.771us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.130s 51.637us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.680s 70.577us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.650s 20.537us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 20.771us 1 1 100.00
rv_timer_csr_aliasing 0.680s 70.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.800s 455.327us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.140s 820.267us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.700s 212.604us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.700s 212.604us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.290s 2343.699us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.520s 11.653us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.520s 12.895us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.110s 76.757us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.110s 76.757us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 70.143us 1 1 100.00
rv_timer_csr_rw 0.560s 20.771us 1 1 100.00
rv_timer_csr_aliasing 0.680s 70.577us 1 1 100.00
rv_timer_same_csr_outstanding 0.600s 45.007us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 70.143us 1 1 100.00
rv_timer_csr_rw 0.560s 20.771us 1 1 100.00
rv_timer_csr_aliasing 0.680s 70.577us 1 1 100.00
rv_timer_same_csr_outstanding 0.600s 45.007us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.710s 270.862us 1 1 100.00
rv_timer_tl_intg_err 0.740s 176.931us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.740s 176.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.530s 26.792us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.540s 217.450us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 21.460s 11584.008us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 11658469164876014891163272292393977589096655308881871501228961859851527030405 86
UVM_INFO @ 217450179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---