Simulation Results: spi_device/1r1w

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.37 %
  • code
  • 91.33 %
  • assert
  • 95.52 %
  • func
  • 72.27 %
  • line
  • 98.89 %
  • branch
  • 98.27 %
  • cond
  • 95.83 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 13.810s 3469.950us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.830s 26.261us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.500s 84.280us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.470s 2256.395us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.600s 353.441us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.820s 55.029us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.500s 84.280us 1 1 100.00
spi_device_csr_aliasing 5.600s 353.441us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.660s 12.657us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.550s 117.001us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.670s 56.101us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.650s 1.402us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.660s 3.802us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.110s 47.297us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.110s 47.297us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.460s 1331.494us 1 1 100.00
spi_device_tpm_sts_read 0.780s 15.858us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.940s 4225.118us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.460s 200.960us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.050s 2242.578us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.050s 2242.578us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.240s 379.918us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.240s 379.918us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.240s 379.918us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.240s 379.918us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.240s 379.918us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.210s 2843.107us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 34.150s 15541.921us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 34.150s 15541.921us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 34.150s 15541.921us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.140s 136.901us 1 1 100.00
spi_device_read_buffer_direct 3.530s 345.310us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 34.150s 15541.921us 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 47.540s 10026.421us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.520s 407.590us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.520s 407.590us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 62.000s 26988.716us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 13.810s 3469.950us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 135.120s 30594.182us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 83.740s 23455.697us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.640s 33.704us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.660s 15.146us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.450s 60.829us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.450s 60.829us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.830s 26.261us 1 1 100.00
spi_device_csr_rw 1.500s 84.280us 1 1 100.00
spi_device_csr_aliasing 5.600s 353.441us 1 1 100.00
spi_device_same_csr_outstanding 3.240s 397.531us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.830s 26.261us 1 1 100.00
spi_device_csr_rw 1.500s 84.280us 1 1 100.00
spi_device_csr_aliasing 5.600s 353.441us 1 1 100.00
spi_device_same_csr_outstanding 3.240s 397.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.820s 175.066us 1 1 100.00
spi_device_tl_intg_err 11.160s 1101.250us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.160s 1101.250us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 50291136271126715364414871811713368670544168439768721030909982720310193654531 81
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 880990 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 880990 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 972177764265973397126422481324368755721842504650637581883456501769263967953 81
UVM_ERROR @ 1239780 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x17b [101111011] vs 0x0 [0])
UVM_ERROR @ 1333780 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1dc [111011100] vs 0x0 [0])
UVM_ERROR @ 1375780 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5b [1011011] vs 0x0 [0])
UVM_ERROR @ 1428780 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x394 [1110010100] vs 0x0 [0])