Simulation Results: sysrst_ctrl

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.25 %
  • code
  • 92.59 %
  • assert
  • 94.16 %
  • func
  • 65.99 %
  • line
  • 97.23 %
  • branch
  • 97.33 %
  • cond
  • 94.69 %
  • toggle
  • 100.00 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.260s 2109.353us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.710s 2481.961us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.450s 2458.234us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.690s 2305.582us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 6.950s 4015.784us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.660s 2045.531us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 8.730s 39217.758us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.490s 2315.294us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.500s 2056.660us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.660s 2045.531us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.490s 2315.294us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 27.180s 30077.404us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 12.300s 68525.486us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.620s 3824.940us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.960s 3262.779us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.460s 2509.149us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.030s 2133.218us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1500.520s 1028826.436us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.650s 2637.800us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 2.810s 3908.204us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 10.030s 40695.143us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 10.650s 11832.516us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.420s 2031.959us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.210s 2021.044us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.610s 2254.738us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.610s 2254.738us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.950s 4015.784us 1 1 100.00
sysrst_ctrl_csr_rw 2.660s 2045.531us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.490s 2315.294us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.870s 4426.801us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.950s 4015.784us 1 1 100.00
sysrst_ctrl_csr_rw 2.660s 2045.531us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.490s 2315.294us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.870s 4426.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 32.010s 22012.308us 1 1 100.00
sysrst_ctrl_tl_intg_err 20.210s 42536.777us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 20.210s 42536.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.550s 6021.142us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  1 test run
sysrst_ctrl_ultra_low_pwr 98180717517288086035351884579639756960136006218513993291841559985792062487392 661
UVM_ERROR @ 3908203559 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3908203559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---