Simulation Results: uart

 
13/08/2026 15:30:29 DVSim: v1.50.1 sha: bf3627c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.93 %
  • code
  • 91.68 %
  • assert
  • 98.85 %
  • func
  • 58.26 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 95.68 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.360s 269.414us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 18.196us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 18.712us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.190s 284.978us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.670s 37.362us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.830s 27.066us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 18.712us 1 1 100.00
uart_csr_aliasing 0.670s 37.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 15.230s 20358.378us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.360s 269.414us 1 1 100.00
uart_tx_rx 15.230s 20358.378us 1 1 100.00
parity_error 2 2 100.00
uart_intr 4.190s 10635.488us 1 1 100.00
uart_rx_parity_err 22.530s 34433.968us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 15.230s 20358.378us 1 1 100.00
uart_intr 4.190s 10635.488us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 15.000s 16308.322us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 112.850s 135004.853us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 8.450s 33344.932us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 4.190s 10635.488us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 4.190s 10635.488us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 4.190s 10635.488us 1 1 100.00
perf 1 1 100.00
uart_perf 499.590s 29339.497us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.460s 3783.587us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.460s 3783.587us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 16.210s 91427.880us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 11.180s 49813.732us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.300s 398.581us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 31.760s 7309.497us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 121.160s 157675.616us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 421.250s 306106.017us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.650s 38.898us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 16.533us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.460s 151.883us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.460s 151.883us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 18.196us 1 1 100.00
uart_csr_rw 0.610s 18.712us 1 1 100.00
uart_csr_aliasing 0.670s 37.362us 1 1 100.00
uart_same_csr_outstanding 0.640s 25.646us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 18.196us 1 1 100.00
uart_csr_rw 0.610s 18.712us 1 1 100.00
uart_csr_aliasing 0.670s 37.362us 1 1 100.00
uart_same_csr_outstanding 0.640s 25.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.730s 67.324us 1 1 100.00
uart_tl_intg_err 1.040s 297.299us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.040s 297.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 36.020s 8333.886us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 15948506061276688725360914258922861097807540947008016609226077702497942038898 94
UVM_ERROR @ 76225180892 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 76233609455 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 76242752303 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 76444609244 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0