Simulation Results: adc_ctrl

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.62 %
  • code
  • 96.82 %
  • assert
  • 96.60 %
  • func
  • 18.44 %
  • line
  • 99.02 %
  • branch
  • 98.39 %
  • cond
  • 94.79 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 3.370s 6001.410us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.730s 1416.126us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.800s 644.252us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 5.590s 26187.907us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.120s 1112.933us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.400s 500.572us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.800s 644.252us 1 1 100.00
adc_ctrl_csr_aliasing 3.120s 1112.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 4.150s 17903.258us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 23.230s 18362.370us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 43.510s 57819.358us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 19.810s 55583.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 9.120s 24234.506us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 23.930s 66253.580us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 79.530s 58811.497us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 15.120s 43889.228us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.440s 2782.882us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 12.310s 30627.231us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 37.860s 96635.757us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 9.470s 74817.007us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.070s 374.158us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.670s 492.159us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.690s 440.768us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.690s 440.768us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.730s 1416.126us 1 1 100.00
adc_ctrl_csr_rw 0.800s 644.252us 1 1 100.00
adc_ctrl_csr_aliasing 3.120s 1112.933us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.960s 4295.922us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.730s 1416.126us 1 1 100.00
adc_ctrl_csr_rw 0.800s 644.252us 1 1 100.00
adc_ctrl_csr_aliasing 3.120s 1112.933us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.960s 4295.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 10.730s 8026.136us 1 1 100.00
adc_ctrl_tl_intg_err 7.550s 8468.460us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 7.550s 8468.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 8.330s 12863.332us 1 1 100.00