Simulation Results: aes/masked

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.93 %
  • code
  • 93.56 %
  • assert
  • 98.23 %
  • func
  • 78.01 %
  • block
  • 94.21 %
  • line
  • 95.91 %
  • branch
  • 87.01 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 93.071us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 95.462us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 59.701us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 92.137us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 352.670us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 70.984us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 66.898us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 92.137us 1 1 100.00
aes_csr_aliasing 2.000s 70.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 95.462us 1 1 100.00
aes_config_error 3.000s 129.728us 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 95.462us 1 1 100.00
aes_config_error 3.000s 129.728us 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 81.639us 1 1 100.00
aes_b2b 12.000s 3621.498us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 95.462us 1 1 100.00
aes_config_error 3.000s 129.728us 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
aes_alert_reset 6.000s 886.054us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 72.005us 1 1 100.00
aes_config_error 3.000s 129.728us 1 1 100.00
aes_alert_reset 6.000s 886.054us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 93.147us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 358.893us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 6.000s 886.054us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 81.639us 1 1 100.00
aes_sideload 3.000s 93.926us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 107.030us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 17.000s 2234.744us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 87.160us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 118.649us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 118.649us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.701us 1 1 100.00
aes_csr_rw 2.000s 92.137us 1 1 100.00
aes_csr_aliasing 2.000s 70.984us 1 1 100.00
aes_same_csr_outstanding 1.000s 65.678us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.701us 1 1 100.00
aes_csr_rw 2.000s 92.137us 1 1 100.00
aes_csr_aliasing 2.000s 70.984us 1 1 100.00
aes_same_csr_outstanding 1.000s 65.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 68.594us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_cipher_fi 2.000s 134.546us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 343.727us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 343.727us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 343.727us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 343.727us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 156.928us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 871.474us 1 1 100.00
aes_tl_intg_err 1.000s 121.621us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 121.621us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 6.000s 886.054us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 343.727us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 343.727us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 95.462us 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
aes_alert_reset 6.000s 886.054us 1 1 100.00
aes_core_fi 2.000s 93.754us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 129.728us 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
aes_core_fi 2.000s 93.754us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 343.727us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 127.045us 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 81.639us 1 1 100.00
aes_sideload 3.000s 93.926us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 127.045us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 127.045us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 127.045us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 127.045us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 127.045us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 81.639us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 187.017us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_cipher_fi 2.000s 134.546us 1 1 100.00
aes_ctr_fi 2.000s 54.390us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 187.017us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_cipher_fi 2.000s 134.546us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 134.546us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 187.017us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_ctr_fi 2.000s 54.390us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 187.017us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_cipher_fi 2.000s 134.546us 1 1 100.00
aes_ctr_fi 2.000s 54.390us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 6.000s 886.054us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_cipher_fi 2.000s 134.546us 1 1 100.00
aes_ctr_fi 2.000s 54.390us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_cipher_fi 2.000s 134.546us 1 1 100.00
aes_ctr_fi 2.000s 54.390us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_ctr_fi 2.000s 54.390us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 187.017us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 187.017us 0 1 0.00
aes_control_fi 2.000s 70.946us 1 1 100.00
aes_cipher_fi 2.000s 134.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 667.034us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 71399440227539251600331666265859251139186964390858990923257914193359569361155 3342
UVM_INFO @ 68594050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 73406107022554509678987677411136540566545497025641761267030428741124243453002 8539
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 10664613832044818128367897513165953933471158740503153534115835616191639276418 268
UVM_INFO @ 667033863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---