Simulation Results: aes/unmasked

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.38 %
  • code
  • 89.13 %
  • assert
  • 97.73 %
  • func
  • 72.28 %
  • block
  • 89.50 %
  • line
  • 91.86 %
  • branch
  • 79.99 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 66.214us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 115.594us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 70.250us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 97.767us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 282.691us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 87.761us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 85.440us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 97.767us 1 1 100.00
aes_csr_aliasing 2.000s 87.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 115.594us 1 1 100.00
aes_config_error 1.000s 72.756us 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 115.594us 1 1 100.00
aes_config_error 1.000s 72.756us 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 55.876us 1 1 100.00
aes_b2b 4.000s 175.222us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 115.594us 1 1 100.00
aes_config_error 1.000s 72.756us 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
aes_alert_reset 4.000s 242.248us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 177.983us 1 1 100.00
aes_config_error 1.000s 72.756us 1 1 100.00
aes_alert_reset 4.000s 242.248us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 69.299us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 414.600us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 242.248us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 55.876us 1 1 100.00
aes_sideload 2.000s 119.422us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 656.801us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 14.000s 1700.070us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 57.939us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 85.548us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 85.548us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 70.250us 1 1 100.00
aes_csr_rw 2.000s 97.767us 1 1 100.00
aes_csr_aliasing 2.000s 87.761us 1 1 100.00
aes_same_csr_outstanding 2.000s 107.036us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 70.250us 1 1 100.00
aes_csr_rw 2.000s 97.767us 1 1 100.00
aes_csr_aliasing 2.000s 87.761us 1 1 100.00
aes_same_csr_outstanding 2.000s 107.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 422.978us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_cipher_fi 1.000s 72.734us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 109.639us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 109.639us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 109.639us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 109.639us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 134.394us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 711.468us 1 1 100.00
aes_tl_intg_err 2.000s 414.339us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 414.339us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 242.248us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 109.639us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 109.639us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 115.594us 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
aes_alert_reset 4.000s 242.248us 1 1 100.00
aes_core_fi 1.000s 64.286us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 1.000s 72.756us 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
aes_core_fi 1.000s 64.286us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 109.639us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 159.863us 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 55.876us 1 1 100.00
aes_sideload 2.000s 119.422us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 159.863us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 159.863us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 159.863us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 159.863us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 159.863us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 55.876us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 124.043us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_cipher_fi 1.000s 72.734us 1 1 100.00
aes_ctr_fi 2.000s 103.002us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 124.043us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_cipher_fi 1.000s 72.734us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 72.734us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 124.043us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_ctr_fi 2.000s 103.002us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 124.043us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_cipher_fi 1.000s 72.734us 1 1 100.00
aes_ctr_fi 2.000s 103.002us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 242.248us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_cipher_fi 1.000s 72.734us 1 1 100.00
aes_ctr_fi 2.000s 103.002us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_cipher_fi 1.000s 72.734us 1 1 100.00
aes_ctr_fi 2.000s 103.002us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_ctr_fi 2.000s 103.002us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 124.043us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 124.043us 0 1 0.00
aes_control_fi 1.000s 48.694us 1 1 100.00
aes_cipher_fi 1.000s 72.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 9.000s 1133.794us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 56856499075639557841746703296602218985217377933574914234547770500368172663749 8639
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:782) scoreboard [scoreboard] # * 1 test run
aes_stress_all 40962263244028029457457119332515008974908023099609656282067421420247213561772 31694
TEST FAILED MESSAGES DID NOT MATCH
0 2d b5 b5 0
1 00 41 41 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 10663602970101828275438229527777491663685265654091761079246989326688277083970 287
UVM_INFO @ 1133793822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---