| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_example_tests | 0 | 4 | 0.00 | |||
| chip_sw_example_flash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_rom | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_manufacturer | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_concurrency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| chip_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| chip_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| chip_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| chip_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke | 0 | 1 | 0.00 | |||
| xbar_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_out | 0 | 1 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_in | 0 | 1 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_irq | 0 | 1 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rx_overflow | 0 | 4 | 0.00 | |||
| chip_sw_uart_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_idx1 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_idx2 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_idx3 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_baud_rate | 0 | 1 | 0.00 | |||
| chip_sw_uart_rand_baudrate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 0 | 2 | 0.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_pin_mux | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_padctrl_attributes | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_mio_dio_val | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_mio_dio_val | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_wake | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_wake | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_retention | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_retention | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_tap_strap_sampling | 0 | 4 | 0.00 | |||
| chip_tap_straps_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_tap_straps_testunlock0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_tap_straps_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_tap_straps_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_instruction_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_outputs | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_rst_inputs | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_rst_inputs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 0 | 10 | 0.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_entropy_reqs_jitter | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_usb_clk_calib | 0 | 1 | 0.00 | |||
| chip_sw_usb_ast_clk_calib | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_ast_alerts | 0 | 2 | 0.00 | |||
| chip_sw_sensor_ctrl_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_ast_status | 0 | 1 | 0.00 | |||
| chip_sw_sensor_ctrl_status | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_smoketest | 0 | 16 | 0.00 | |||
| chip_sw_aes_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_usbdev_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_plic_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_timer_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_smoketest | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_functests | 0 | 1 | 0.00 | |||
| rom_keymgr_functest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_boot | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_secure_boot | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_raw_unlock | 0 | 1 | 0.00 | |||
| rom_raw_unlock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_idle_load | 0 | 1 | 0.00 | |||
| chip_sw_power_idle_load | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_sleep_load | 0 | 1 | 0.00 | |||
| chip_sw_power_sleep_load | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 0 | 1 | 0.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_inject_scramble_seed | 0 | 1 | 0.00 | |||
| chip_sw_inject_scramble_seed | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_base_random_sequence | 0 | 1 | 0.00 | |||
| xbar_random | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_random_delay | 0 | 6 | 0.00 | |||
| xbar_smoke_zero_delays | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke_large_delays | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke_slow_rsp | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_random_zero_delays | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_random_large_delays | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_random_slow_rsp | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_unmapped_address | 0 | 2 | 0.00 | |||
| xbar_unmapped_addr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_error_and_unmapped_addr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_error_cases | 0 | 2 | 0.00 | |||
| xbar_error_random | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_error_and_unmapped_addr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_all_access_same_device | 0 | 2 | 0.00 | |||
| xbar_access_same_device | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_access_same_device_slow_rsp | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_all_hosts_use_same_source_id | 0 | 1 | 0.00 | |||
| xbar_same_source | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_stress_all | 0 | 2 | 0.00 | |||
| xbar_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_stress_all_with_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_stress_with_reset | 0 | 2 | 0.00 | |||
| xbar_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_stress_all_with_reset_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_smoke | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_output | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_output | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 5 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init | 0 | 3 | 0.00 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_static_critical | 0 | 1 | 0.00 | |||
| rom_e2e_static_critical | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_adc_ctrl_debug_cable_irq | 0 | 1 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc | 0 | 2 | 0.00 | |||
| chip_sw_aes_enc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_entropy | 0 | 1 | 0.00 | |||
| chip_sw_aes_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_idle | 0 | 1 | 0.00 | |||
| chip_sw_aes_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_sideload | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_sideload_aes | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_escalations | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_all_escalation_resets | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_irqs | 0 | 3 | 0.00 | |||
| chip_plic_all_irqs_0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_plic_all_irqs_10 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_plic_all_irqs_20 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_entropy | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_crashdump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_ping_timeout | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_ping_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_ping_ok | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_ping_ok | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wakeup_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_idle_trans | 0 | 4 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_trans | 0 | 4 | 0.00 | |||
| chip_sw_clkmgr_off_aes_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_kmac_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_otbn_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_peri | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_off_peri | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_div | 0 | 7 | 0.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_outputs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_external_clk_src_for_lc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw | 0 | 2 | 0.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 0 | 10 | 0.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_entropy_reqs_jitter | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_extended_range | 0 | 11 | 0.00 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_init_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_sleep_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_reset_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_reset_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_alert_handler_clock_enables | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_cmd | 0 | 1 | 0.00 | |||
| chip_sw_entropy_src_csrng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 1 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_lc_hw_debug_en | 0 | 1 | 0.00 | |||
| chip_sw_csrng_lc_hw_debug_en_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_known_answer_tests | 0 | 1 | 0.00 | |||
| chip_sw_csrng_kat_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_entropy_reqs | 0 | 3 | 0.00 | |||
| chip_sw_csrng_edn_concurrency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_ast_rng_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_entropy_reqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_ast_rng_req | 0 | 1 | 0.00 | |||
| chip_sw_entropy_src_ast_rng_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_csrng | 0 | 1 | 0.00 | |||
| chip_sw_entropy_src_csrng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_known_answer_tests | 0 | 1 | 0.00 | |||
| chip_sw_entropy_src_kat_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_init | 0 | 1 | 0.00 | |||
| chip_sw_flash_init | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_host_access | 0 | 2 | 0.00 | |||
| chip_sw_flash_ctrl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_ops | 0 | 2 | 0.00 | |||
| chip_sw_flash_ctrl_ops | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_ops_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_rma_unlocked | 0 | 1 | 0.00 | |||
| chip_sw_flash_rma_unlocked | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_scramble | 0 | 1 | 0.00 | |||
| chip_sw_flash_init | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_idle_low_power | 0 | 1 | 0.00 | |||
| chip_sw_flash_ctrl_idle_low_power | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_keymgr_seeds | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_lc_creator_seed_sw_rw_en | 0 | 1 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_creator_seed_wipe_on_rma | 0 | 1 | 0.00 | |||
| chip_sw_flash_rma_unlocked | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_lc_owner_seed_sw_rw_en | 0 | 1 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_rd_en | 0 | 1 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_wr_en | 0 | 1 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_lc_seed_hw_rd_en | 0 | 1 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_lc_escalate_en | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_prim_tl_access | 0 | 1 | 0.00 | |||
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_clock_freqs | 0 | 1 | 0.00 | |||
| chip_sw_flash_ctrl_clock_freqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_flash_crash_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 0 | 1 | 0.00 | |||
| chip_sw_flash_crash_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc | 0 | 2 | 0.00 | |||
| chip_sw_hmac_enc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_idle | 0 | 1 | 0.00 | |||
| chip_sw_hmac_enc_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_all_configurations | 0 | 1 | 0.00 | |||
| chip_sw_hmac_oneshot | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_multistream_mode | 0 | 1 | 0.00 | |||
| chip_sw_hmac_multistream | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 0 | 3 | 0.00 | |||
| chip_sw_i2c_host_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx_idx1 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx_idx2 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_device_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_device_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_key_derivation | 0 | 2 | 0.00 | |||
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_sideload_kmac | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_sideload_kmac | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_sideload_aes | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_sideload_aes | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_sideload_otbn | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_sideload_otbn | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_enc | 0 | 3 | 0.00 | |||
| chip_sw_kmac_mode_cshake | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_keymgr | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_lc | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_rom | 0 | 1 | 0.00 | |||
| chip_sw_kmac_app_rom | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_entropy | 0 | 1 | 0.00 | |||
| chip_sw_kmac_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_idle | 0 | 1 | 0.00 | |||
| chip_sw_kmac_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_jtag_access | 0 | 3 | 0.00 | |||
| chip_tap_straps_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_tap_straps_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_tap_straps_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg0 | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transitions | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_kmac_req | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_key_div | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_key_derivation_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_broadcast | 0 | 22 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_rma_unlocked | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_execution_main | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_tap_straps_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_tap_straps_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_tap_straps_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_scrap | 0 | 4 | 0.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_test_locked | 0 | 2 | 0.00 | |||
| chip_sw_lc_walkthrough_testunlocks | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough | 0 | 5 | 0.00 | |||
| chip_sw_lc_walkthrough_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 0 | 3 | 0.00 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_volatile_raw_unlock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_op | 0 | 2 | 0.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_rnd_entropy | 0 | 1 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_urnd_entropy | 0 | 1 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_idle | 0 | 1 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_mem_scramble | 0 | 1 | 0.00 | |||
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_otp_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_keys | 0 | 5 | 0.00 | |||
| chip_sw_flash_init | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_entropy | 0 | 5 | 0.00 | |||
| chip_sw_flash_init | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program_error | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_program_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_hw_cfg0 | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals | 0 | 6 | 0.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_prim_tl_access | 0 | 1 | 0.00 | |||
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_dai_lock | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_por_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_por_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_normal_sleep_por_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0 | 2 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_wdog_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sysrst_ctrl_reset | 0 | 2 | 0.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_all_reset_reqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_b2b_sleep_reset_req | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_disabled | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_access | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_non_sys_reset_info | 0 | 4 | 0.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sys_reset_info | 0 | 1 | 0.00 | |||
| chip_rv_dm_ndm_reset_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_cpu_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_req_reset | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_sw_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_alert_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_rst | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_sw_rst | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_alert_handler_reset_enables | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_nmi_irq | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_rnd | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_rnd | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_address_translation | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_address_translation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_fault_dump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_double_fault | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_mcounteren_writable | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_mcounteren_writable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_csr_rw | 0 | 1 | 0.00 | |||
| chip_jtag_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_mem_access | 0 | 1 | 0.00 | |||
| chip_jtag_mem_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_ndm_reset_req | 0 | 1 | 0.00 | |||
| chip_rv_dm_ndm_reset_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_jtag_tap_sel | 0 | 1 | 0.00 | |||
| chip_tap_straps_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0 | 1 | 0.00 | |||
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_all_irqs | 0 | 3 | 0.00 | |||
| chip_plic_all_irqs_0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_plic_all_irqs_10 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_plic_all_irqs_20 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_sw_irq | 0 | 1 | 0.00 | |||
| chip_sw_plic_sw_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_timer | 0 | 1 | 0.00 | |||
| chip_sw_rv_timer_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_flash_mode | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_tpm | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_tpm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_spi_host_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_scrambled_access | 0 | 2 | 0.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_sram_ret_contents | 0 | 2 | 0.00 | |||
| chip_sw_sleep_sram_ret_contents_no_scramble | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_sram_ret_contents_scramble | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_execution | 0 | 1 | 0.00 | |||
| chip_sw_sram_ctrl_execution_main | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_lc_escalation | 0 | 2 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_reset | 0 | 2 | 0.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_inputs | 0 | 1 | 0.00 | |||
| chip_sw_sysrst_ctrl_inputs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_outputs | 0 | 1 | 0.00 | |||
| chip_sw_sysrst_ctrl_outputs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_in_irq | 0 | 1 | 0.00 | |||
| chip_sw_sysrst_ctrl_in_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_sleep_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_sleep_reset | 0 | 1 | 0.00 | |||
| chip_sw_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_ec_rst_l | 0 | 1 | 0.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_flash_wp_l | 0 | 1 | 0.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 0 | 2 | 0.00 | |||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_vbus | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_vbus | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_pullup | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_pullup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_aon_pullup | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_aon_pullup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_setup_rx | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_setuprx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_config_host | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_config_host | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_pincfg | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_pincfg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_dpi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_toggle_restore | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_toggle_restore | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 0 | 1 | 0.00 | |||
| chip_sw_aes_masking_off | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_coremark | 0 | 1 | 0.00 | |||
| chip_sw_coremark | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_max_load | 0 | 1 | 0.00 | |||
| chip_sw_power_virus | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 1 | 0.00 | |||
| rom_e2e_self_hash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter_cycle_measurements | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_jitter_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_boot_mode | 0 | 1 | 0.00 | |||
| chip_sw_edn_boot_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_auto_mode | 0 | 1 | 0.00 | |||
| chip_sw_edn_auto_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_sw_mode | 0 | 1 | 0.00 | |||
| chip_sw_edn_sw_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_kat | 0 | 1 | 0.00 | |||
| chip_sw_edn_kat | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_memory_protection | 0 | 1 | 0.00 | |||
| chip_sw_flash_ctrl_mem_protection | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_deep_sleep_wake_up | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_all_resets | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_alerts | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tick_configuration | 0 | 1 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| counter_wrap | 0 | 1 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pinmux_sleep_retention | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_watermarks | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_stream | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_stream | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 11 | 0.00 | |||
| chip_sival_flash_info_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_rot_auth_config | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_descrambling | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_lowpower_cancel | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_wake_5_bug | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_flash_scrambling_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| ate_bootstrap_flash_erase | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| ate_bootstrap_one_frame | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| ate_bootstrap_disjoint | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 327 test runs | |||
| chip_csr_bit_bash | 15677233139106475557577807223391436458252702361826291428406904188635609124179 | None | ||
| chip_csr_aliasing | 40217543751529368821851370153902423746781496406396297894463207182071719861630 | None | ||
| chip_same_csr_outstanding | 1262008224076445730094571100771574761426915396559287055784345153025292165567 | None | ||
| chip_sw_example_flash | 48162056783057772413768957222780958034830643053864193052829502458225598439753 | None | ||
| chip_sw_example_rom | 51811159068184338314188134201583328821778171298761514333849996290182905771900 | None | ||
| chip_sw_example_manufacturer | 75082574054795579179573155670062062313750208399311117774996101262097899703445 | None | ||
| chip_sw_example_concurrency | 32226990098835231150176165624856536584536869571064044809116664278983601964912 | None | ||
| chip_sival_flash_info_access | 1819927200734985473081506758575692141698390549217789014665004019523345733081 | None | ||
| chip_sw_all_escalation_resets | 88668061072268745934165708098033695219632998161643797367372363426174951394431 | None | ||
| chip_sw_rstmgr_rst_cnsty_escalation | 101820616000735919098707279062851629230321960815762847480364401988909338546221 | None | ||
| chip_sw_data_integrity_escalation | 53288249412117359107270952614696239263807255515484380031585338646214357727287 | None | ||
| chip_sw_sleep_pin_mio_dio_val | 27576584536395631382048039121718194683303693895876500590586540457683471599104 | None | ||
| chip_sw_sleep_pin_wake | 17479176178962447062771202525892344710075106759867805630100031354473722834025 | None | ||
| chip_sw_sleep_pin_retention | 78491978336495879130462809295281054980812211099286546786356150689391015478883 | None | ||
| chip_sw_uart_tx_rx | 98788724491387191920934339741258192755217580179343211207355277779071469348357 | None | ||
| chip_sw_uart_tx_rx_idx1 | 58642035836229445563316476194021941845848283157523780611462218107096921164563 | None | ||
| chip_sw_uart_tx_rx_idx2 | 51142530218165229420589419605357851153705835016402651329665183937613403014110 | None | ||
| chip_sw_uart_tx_rx_idx3 | 28601302072259969507835257160043023667857225760175268156993627596249942726224 | None | ||
| chip_sw_uart_tx_rx_bootstrap | 46154070091007982792387175814993238646403090067075789879392684626866051200205 | None | ||
| chip_sw_usbdev_vbus | 48804545202347378740102997903052520677872721421688697199232811691827819423800 | None | ||
| chip_sw_usbdev_dpi | 60315890294429630441590678278813295198166382855915699801994548309933994699584 | None | ||
| chip_sw_usbdev_pullup | 42158047236397505585188241394407680223635941298543450852478684155933244867473 | None | ||
| chip_sw_usbdev_aon_pullup | 110095245307068805020093546044709357725246874127976840916708374510855149894040 | None | ||
| chip_sw_usbdev_setuprx | 115123387937448950867749808626885145047055353373338230669106171856847868927979 | None | ||
| chip_sw_usbdev_config_host | 19629707326301420476144924522382365642242048652662780664407336606722408558161 | None | ||
| chip_sw_usbdev_pincfg | 46311419230185428382886323488480883476328748403849991789894863620690666638557 | None | ||
| chip_sw_usbdev_stream | 51334416592147817961741041831055250479706644113174880602203365219112152874074 | None | ||
| chip_sw_usbdev_toggle_restore | 71913925016250339802180724587448213891729485307225504317187436139042009796655 | None | ||
| chip_sw_inject_scramble_seed | 19644700595952828732697426625159368311675872295386484587856466347876438607103 | None | ||
| chip_sw_exit_test_unlocked_bootstrap | 109177086847635818607948914276471678877691704657914558609149151764779839682191 | None | ||
| chip_sw_uart_rand_baudrate | 96436485879695403958758488716718527772638493356990267495999079507621156974245 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq | 95801272408490386928635011545668811127468930016163384817074968338048467992862 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 102826740937104832989183702162158332136252359269050288774331985803040153529574 | None | ||
| chip_sw_i2c_host_tx_rx | 71734060363407091038166962496519627557092204734094957975522078644909309439538 | None | ||
| chip_sw_i2c_host_tx_rx_idx1 | 28631887177538834959683105151636356763372160498795371564127400096997039517627 | None | ||
| chip_sw_i2c_host_tx_rx_idx2 | 2449469291902001076220939964345968362013637935232269084911033104189975925937 | None | ||
| chip_sw_i2c_device_tx_rx | 7883560203714799652671054495666522907915524351361498467515717978734499824421 | None | ||
| chip_sw_spi_device_tpm | 114251494863579036320158474060908971381657536879529408284716993609741249217154 | None | ||
| chip_sw_spi_host_tx_rx | 26873795344276051457595928944419263976917606769437047379737376255724357558660 | None | ||
| chip_sw_spi_device_pinmux_sleep_retention | 42875836620334478666037251331793755011577266093416906638414889575053294193707 | None | ||
| chip_sw_spi_device_pass_through | 54036595245521361199752857703112601563049127943902985049474347300960897881443 | None | ||
| chip_sw_spi_device_pass_through_collision | 2817030786599960982349482179544763414887361698775602167048348099265620198371 | None | ||
| chip_sw_gpio | 26418265252751195077083884571143757653535077680562622408192428839867983207169 | None | ||
| chip_sw_flash_ctrl_ops | 84986976223377484190524917951457060301714158646730310688708058001146342316931 | None | ||
| chip_sw_flash_ctrl_ops_jitter_en | 32615747727981192666356901853710167298554891886870612513915691600276467348795 | None | ||
| chip_sw_flash_ctrl_lc_rw_en | 107919974486213560213899479821026055633978945067254721178570455357726832834710 | None | ||
| chip_sw_flash_ctrl_access | 51549691125272926776207495976254688253856717110090262875654021921693742204745 | None | ||
| chip_sw_flash_ctrl_access_jitter_en | 8990130604567329915330214407250614655083664902645704977319605599051404730393 | None | ||
| chip_sw_flash_ctrl_idle_low_power | 78554946307791657506118330318083460944955915227364393369921853030104792279780 | None | ||
| chip_sw_flash_init | 37796971570045775378924709665459879790066488052107176840818096778084923149502 | None | ||
| chip_sw_flash_rma_unlocked | 76183160682881212146574293826689355823027900050203205206395262795047283578727 | None | ||
| chip_sw_flash_ctrl_clock_freqs | 30049036574793596050561005588006303853243738400234672877600267996072185242204 | None | ||
| chip_sw_kmac_entropy | 111952329242293061526504134297417904756835557942483073702774573558278751113373 | None | ||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 9074194579918368833328695237579745250540077206507909187999075514135403885222 | None | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 68839532901708834597181103407369638902908549330046730192077676087526005387494 | None | ||
| chip_sw_otp_ctrl_lc_signals_dev | 2758798499125891251438265190645641337109398184621226175915730423173568264021 | None | ||
| chip_sw_otp_ctrl_lc_signals_prod | 76125433763054303782263389134390754576474918185273111205417377611975119317615 | None | ||
| chip_sw_otp_ctrl_lc_signals_rma | 58027856069822741605417425378243500677179501055344965695992194750378256546239 | None | ||
| chip_sw_otp_ctrl_escalation | 15246321846542118660694518579529329530666304489441293435179831665625697075904 | None | ||
| chip_sw_otp_ctrl_dai_lock | 9932712572274657923520428230587996099818215347182066247599811609623516844378 | None | ||
| chip_sw_otp_ctrl_rot_auth_config | 57706622664221539844557821022499929856793032787694034716750778241737498727376 | None | ||
| chip_sw_otp_ctrl_descrambling | 68450453915107006032265231774463055267610822153592684515836761327204712493312 | None | ||
| chip_sw_lc_ctrl_transition | 34449324013134130958793287243166907171106683148951022491034121038713040643464 | None | ||
| chip_sw_lc_ctrl_rma_to_scrap | 59111115671056026243348377338613808451588699151100694185095420240190956517282 | None | ||
| chip_sw_lc_ctrl_raw_to_scrap | 52304155223117973290387180518344505008582613081235336876276677269635294923936 | None | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 75094396189382775144602069006288277809476994019540674715047091675417125258103 | None | ||
| chip_sw_lc_ctrl_rand_to_scrap | 102128200493415633286164247039241498392465241210600675957457385069032815028220 | None | ||
| chip_sw_lc_walkthrough_dev | 15155836717152802764604128033785327453400580534078627604107777853839905926321 | None | ||
| chip_sw_lc_walkthrough_prod | 23292156923916452755540483578891532463773653082597073628530309946901158199112 | None | ||
| chip_sw_lc_walkthrough_prodend | 49005347195282851177157824226860400132035019336177074613008747985680350725540 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock | 30184900472541757390524698617874532519261950739621670440346272734642413631947 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 114353583877457329342349774454261156316404841387311737837377007224477894831206 | None | ||
| chip_sw_lc_walkthrough_rma | 106816873686091002118701828189705070585161095438426109318985284258202962355526 | None | ||
| chip_sw_lc_walkthrough_testunlocks | 29651812175456403551976751227796343514507312708282117020159002866218346636088 | None | ||
| chip_sw_rstmgr_sw_req | 21330019386990442279896059784161115336625434741809457557405515532769231980858 | None | ||
| chip_sw_rstmgr_sw_rst | 56009864622437291123863470739387706884601308613293242187570050203218247368768 | None | ||
| chip_sw_rstmgr_alert_info | 48484266878352476501617580594712003070865586653677515269794218106218100516421 | None | ||
| chip_sw_rstmgr_cpu_info | 114417436249734324242404097384394553326759920245146497861390641112349952780750 | None | ||
| chip_sw_pwrmgr_full_aon_reset | 48014211632514162644269206236060275559529182656504871044724461584594168365609 | None | ||
| chip_sw_pwrmgr_main_power_glitch_reset | 73882228734075206463569676874033872003089903258702788157852095362062556181958 | None | ||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 29729225131074505293191994152416201276439090936159544533116263363998308555421 | None | ||
| chip_sw_pwrmgr_all_reset_reqs | 712076091549286082526928548637697268576987193978866058493759702540712759868 | None | ||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 8954621234389703416991947369628214043014056688042993585894096815035737736103 | None | ||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 31871874262467497603300153756750854331903777557805856077862505747731683225304 | None | ||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 38461514949229601053976671099499382146788719171751394719831256161774084088822 | None | ||
| chip_sw_pwrmgr_deep_sleep_por_reset | 87856944571986945400306911062891676250338586517764804401818091769162517508155 | None | ||
| chip_sw_pwrmgr_normal_sleep_por_reset | 56338687938811369414468164078910696854072624977058326776808083623326059298016 | None | ||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 98085529230687105346826981261753580811068042722106031959653366829713118128787 | None | ||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 88085521842279636872671984085698180475953141041983945275120131795777626922896 | None | ||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 93210050127226341824012079455214229888189575913840776033296470452216976292678 | None | ||
| chip_sw_pwrmgr_sleep_disabled | 43757315359882703516914829724025388439461190815779731074175636671281413104736 | None | ||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 56227849243753912992402628289280265058806179496749588741360999412264863984583 | None | ||
| chip_sw_rv_timer_irq | 66818527119778890334662814871222997103935690796883142125740389051817457108824 | None | ||
| chip_sw_rv_timer_systick_test | 42939807916347003639929905795566141164001825932968019519580395123398418375952 | None | ||
| chip_sw_sysrst_ctrl_inputs | 90205005528037460373517424976668714863271357309585670399171945695429215509555 | None | ||
| chip_sw_sysrst_ctrl_in_irq | 26474718423944205743008994150016099669351020716979485984165758912171445702980 | None | ||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 70762299258046503658422569298897777947390714965350680176515002963487459364801 | None | ||
| chip_sw_sysrst_ctrl_reset | 17115389363084947999163059367698257827266909806516543851465538798970516886809 | None | ||
| chip_sw_sysrst_ctrl_outputs | 31953517312134955269050915782036898673314724707823857193926178037155908236339 | None | ||
| chip_sw_sysrst_ctrl_ec_rst_l | 20442831623189558572007910665313240794604474798035271075080175226394503637631 | None | ||
| chip_sw_aon_timer_irq | 54799517005259895397992413163761955602534167709159085905496151490941235971305 | None | ||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 63379157345454714509250145755415313063910818055160012151235191137565889152278 | None | ||
| chip_sw_aon_timer_wdog_bite_reset | 46789973070137208033298788620443766486160061491625675283650122864390575855723 | None | ||
| chip_sw_pwrmgr_wdog_reset | 38279058234582934076300578349024990965785889433771566772764133037308251459410 | None | ||
| chip_sw_aon_timer_wdog_lc_escalate | 24928509403748224462962692238085386839075664698344088484269338692755003667488 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 4724479809062592693652806908222391576780641662471263296783634913250741047361 | None | ||
| chip_sw_otbn_randomness | 51144613859981280844797769916262563902346796502188329324227279435856294123617 | None | ||
| chip_sw_otbn_ecdsa_op_irq | 388914961486304323954124480562043887647026998243769708918113898848804967637 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 31367963435380067135664622623175386694544227753919698570040056422829759162609 | None | ||
| chip_sw_otbn_mem_scramble | 7143377219675860976795040411518742419980193420711462470144392937181532392449 | None | ||
| chip_sw_rv_core_ibex_rnd | 53006688847017162760997808369922222669344275329238290359406096168829570837812 | None | ||
| chip_sw_rv_core_ibex_nmi_irq | 4781603358843813421283553659292127373297056204200627919107794116228117114193 | None | ||
| chip_sw_aes_enc | 89218819028092923147510603715602522171014368668628634352427356745102176211009 | None | ||
| chip_sw_aes_enc_jitter_en | 87896982326557785978621085953496007548873017061924727330400386625051448096940 | None | ||
| chip_sw_aes_idle | 63476734040115284211071747473967383709302246529818928401844579714279027981160 | None | ||
| chip_sw_aes_masking_off | 80889088509210020041034894887638368495907602564786730682455322461144041109721 | None | ||
| chip_sw_alert_test | 7591898622489147943918097916618593931736833755687980104219406759361949669300 | None | ||
| chip_sw_alert_handler_escalation | 47110809375697704688976625239221205782375914768617221103008322432580263839927 | None | ||
| chip_sw_alert_handler_ping_timeout | 40940927144081421893930872843927977189206928200155906408502722774452925736072 | None | ||
| chip_sw_alert_handler_ping_ok | 70994013580353213981415416222138272563978749593223361075839899813214906092422 | None | ||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 30051515446172495738754165716076189615975922809024071012149490122515848115356 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 27286267399412250828042200007711756370333868236501403905900767981369693613293 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 57176352110241021407422917198262116933279317692442522641098522289519203314846 | None | ||
| chip_sw_alert_handler_lpg_clkoff | 20326572195907000990367093937890489144383109595075438775489054565570162050298 | None | ||
| chip_sw_alert_handler_lpg_reset_toggle | 5461114315736111124871637834133198069594534830984016499298978880480928733147 | None | ||
| chip_sw_alert_handler_entropy | 21343848949037894064242374267775976674745678561447834755775461271244840313126 | None | ||
| chip_sw_aes_entropy | 19783795035887464405361453049589373096801764649667033991175071730773289434109 | None | ||
| chip_sw_entropy_src_kat_test | 40523934972640642642600026321911949490653731872989458123535904834929304924558 | None | ||
| chip_sw_edn_auto_mode | 35272271856796523978235235541592955045410891656507468052372645827008942429251 | None | ||
| chip_sw_edn_boot_mode | 114265236056652192213442312471095773889814615220242970820605061999795656859778 | None | ||
| chip_sw_edn_kat | 44065805481159674014953822186464168186029232113632208471098514894991864290839 | None | ||
| chip_sw_edn_sw_mode | 109478778521625536218265273522762394338936244682335863720502170404636150611145 | None | ||
| chip_sw_csrng_lc_hw_debug_en_test | 10913142407000541922779527505665640792868281301257053906401850152564750618570 | None | ||
| chip_sw_csrng_edn_concurrency | 35104508392938249906348933107226195275962744129882196994895627284154722783790 | None | ||
| chip_sw_csrng_kat_test | 25145843264321689959515897047986643592989525728215470818583169059605053729786 | None | ||
| chip_sw_csrng_fuse_en_sw_app_read_test | 31206826591530089470332232538541131618207900822413590899156376580545026481941 | None | ||
| chip_sw_entropy_src_ast_rng_req | 61925901118871416070631895357759534472573090933497682317435144598775203734737 | None | ||
| chip_sw_entropy_src_csrng | 52681981883877060715337013753225054319157750348931466153305004856201264076689 | None | ||
| chip_sw_edn_entropy_reqs | 13316100887071584257312922124605393563713666440018162355773225552950366227109 | None | ||
| chip_sw_edn_entropy_reqs_jitter | 23642618514994881239975340025692191192193837992698684525875346851771919006120 | None | ||
| chip_sw_hmac_enc | 107379062798406575426777055382435622401510710363524833141533763672546925125962 | None | ||
| chip_sw_hmac_enc_jitter_en | 97013868663981058205182703639130943451000727597124247462232180562951779670490 | None | ||
| chip_sw_hmac_enc_idle | 101526950067723909614343526009466543878233250600745151566674537010009900242721 | None | ||
| chip_sw_hmac_oneshot | 50645943452891374808021134958894996476205452385199014344760923003328319893254 | None | ||
| chip_sw_hmac_multistream | 36325156003090467889730464808828036430142268393031831727697539288099657504963 | None | ||
| chip_sw_keymgr_key_derivation | 56376696808392230673703144078142930760974624214621400721114913003265134725888 | None | ||
| chip_sw_keymgr_key_derivation_prod | 52632118564144150127733855176947786282623905256881280661831452336453387109878 | None | ||
| chip_sw_keymgr_key_derivation_jitter_en | 31381181298362700072872412491329049358267561611110105286355282175009861687687 | None | ||
| chip_sw_keymgr_sideload_kmac | 102181645922462303760379586567910268674295074450779829056640279703272896299523 | None | ||
| chip_sw_keymgr_sideload_aes | 7796007336684525423498071208725283203107116272628307097902837204383645731163 | None | ||
| chip_sw_keymgr_sideload_otbn | 41698196494622064506254383266013709363073776904715687739246992267761003662808 | None | ||
| chip_sw_kmac_mode_cshake | 21040129983329506624324601825004309031346429723900843634000340440669480591518 | None | ||
| chip_sw_kmac_mode_kmac | 90803513119294522799919322615530087373572769249418570815939485409782912430711 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en | 69370363437390641717957298831023690694566974396094583219286859145945183664211 | None | ||
| chip_sw_kmac_app_rom | 3947167516247884715957992437181238504781199925755014269462475945833536144440 | None | ||
| chip_sw_kmac_idle | 82357163071651875401867425835404284508811696714610982446899161750078738351787 | None | ||
| chip_sw_rom_ctrl_integrity_check | 110480883635666471681522130833356983354196966974557826975848164576517973519328 | None | ||
| chip_sw_sram_ctrl_scrambled_access | 39978489766231014957420024418528692519141065630426505998674106299388942541148 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 42703696722661006879984141810962012045425923823360605678519230714754279907185 | None | ||
| chip_sw_sram_ctrl_execution_main | 65307052838634277098130284544215460921009904539716945409956503316587543763299 | None | ||
| chip_sw_sleep_sram_ret_contents_no_scramble | 42206646799245182247067182100123315690056110571342716100030907821088666336096 | None | ||
| chip_sw_sleep_sram_ret_contents_scramble | 103132503255848355424304752889873927742391312788673621070445878801145441827823 | None | ||
| chip_sw_sensor_ctrl_alert | 99101845695971101308517400507139909345028938795294481885506889191317079203104 | None | ||
| chip_sw_sensor_ctrl_status | 1343713803981114274425426960297789582402642744311974731772534980417356953800 | None | ||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 60268191013869257669126803218823829683461052554553983160989259071094328892258 | None | ||
| chip_sw_coremark | 74832643839913793665390797254856989709007375914545403928696349670057809700200 | None | ||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 43388657013947675073562555292785061511919485118053350653327820609014132107428 | None | ||
| chip_tl_errors | 4319965085134475202522841378329778519958408440335855844630290272707951723672 | None | ||
| chip_prim_tl_access | 26298779597475997565533253361055592324749315129371096198012465052608355335507 | None | ||
| chip_plic_all_irqs_0 | 28111840417985293412952116036530000364914957238083078271392333709942169761472 | None | ||
| chip_plic_all_irqs_10 | 97624630636707085411888095511390172272578305431116570609908027510168296460552 | None | ||
| chip_plic_all_irqs_20 | 10814248319967307519581000161366051176454269611930835806291575700436550387589 | None | ||
| chip_sw_plic_sw_irq | 95241272049529158466520308985498925105124943846917518173002338606121262489382 | None | ||
| chip_sw_clkmgr_off_peri | 12766044626368827922411302552953012417169605497104199801094951932435072728570 | None | ||
| chip_sw_clkmgr_off_aes_trans | 83151182534874657717796503721716070903079077896015695570173857352995036905399 | None | ||
| chip_sw_clkmgr_off_hmac_trans | 36265927761799198678094656869128951793618742760146653146414906961439114606600 | None | ||
| chip_sw_clkmgr_off_kmac_trans | 32798173737764907634136824881108300093001130489895763563647896038272347138069 | None | ||
| chip_sw_clkmgr_off_otbn_trans | 108162270706110019534055161617358358881561127508763641606498929503134387094282 | None | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 33361760960651943008862977520011329899862593832844888141588750953317555843464 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 55657791773001940828463750866392816624572271913605755507398584339277279019028 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 15913100784166736730609431046038365093941029134339629615832310334872701866146 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 56752343387736100320300394844529688917294371565440039298993619384029379731927 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 7491151069171836785460657109425003340500418611922257448389666853125849078363 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 38150849090055721865493817339728412793890091272691243683539386832944292718110 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 88431024029148831334316610814233752445631011983872280776311532813822415661421 | None | ||
| chip_sw_clkmgr_reset_frequency | 2117780499238285428404468453675354038842693611707971756095808473500003786466 | None | ||
| chip_sw_clkmgr_jitter_frequency | 14906708313638764300564364359920225075162982635436597181009953196887612447550 | None | ||
| chip_sw_clkmgr_jitter | 46337983583722961261197876112177915033369232450995822791598057754957387165169 | None | ||
| chip_sw_clkmgr_sleep_frequency | 7654299580868987070118626549515877799313677194563027939367891161976319649954 | None | ||
| chip_jtag_csr_rw | 57282326053817439008536797454762262924925798511267672129800639962130687264125 | None | ||
| chip_jtag_mem_access | 90138441252647701911707545664471947281214528571555162450712719646899070121887 | None | ||
| chip_sw_ast_clk_outputs | 64201001303091658418345602941639188427913482066676523486374039369040712378672 | None | ||
| chip_sw_lc_ctrl_program_error | 25628349760628518434659421665620939492662742172832517503392707911630304137534 | None | ||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 78973244255646212095678946359237912330120569619465510804740948800705232261396 | None | ||
| chip_sw_pwrmgr_lowpower_cancel | 87227051386087263195858072938309754283282391676483050231702374948305814289705 | None | ||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 31327973686472908116666375400966474299739063387586835724497908888712730596062 | None | ||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 74125030311368523262946428911850708280333039457984288327189736856886419620168 | None | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 64122393405871733925453116783685258277392389363523587659177791319242962336366 | None | ||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 101158154297797459604540493074144518030109697535686333128486370102332821801414 | None | ||
| chip_rv_dm_ndm_reset_req | 30999357628428597878012550450027193884866500104909686241474870456455647985099 | None | ||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 89394343974843571657190417264316510545324571672293350561338913141097230492478 | None | ||
| chip_sw_rv_dm_access_after_wakeup | 36535710745463053416261285646135568519828312238636118718731283460104879312632 | None | ||
| chip_sw_rv_dm_access_after_escalation_reset | 13989300537135838631419755234338661819870692629469188681551469042404763419974 | None | ||
| chip_tap_straps_dev | 33373777027275012837408268400489839291861175559019132992188271414910383335629 | None | ||
| chip_tap_straps_testunlock0 | 79691000082859703275045000688602858224438316301403555482815209657292571553925 | None | ||
| chip_tap_straps_rma | 86231430403922595656606332361587334343432751228231380004999083850175342985251 | None | ||
| chip_tap_straps_prod | 114516434880505142252095794959681768806180388179665219872987149631173098010770 | None | ||
| chip_rv_dm_lc_disabled | 108123669694371582530110055497784211667055534895409642918216916265337697663049 | None | ||
| chip_sw_rv_core_ibex_address_translation | 20049012724350451809313400648267627937575402556984531483345168539333776506600 | None | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 45079278085731904887671952880102483890394144073397014471496289007949222841471 | None | ||
| chip_sw_rv_core_ibex_icache_invalidate | 57686386779857904752153067476236734557486940827405383731436976325731126986362 | None | ||
| chip_sw_rv_core_ibex_mcounteren_writable | 82462592396439813947010582235957517410010399868501345925247353332767777752087 | None | ||
| chip_sw_usb_ast_clk_calib | 41314433946313069267591098800253152256243728627375085468941784926588397055519 | None | ||
| chip_sw_flash_crash_alert | 60987526289542671091228648719955111816116935418669006167955833970948014748791 | None | ||
| chip_sw_flash_ctrl_write_clear | 76700091526901205590342855546482219651637290384394981571104443912386153178442 | None | ||
| chip_padctrl_attributes | 87892445849784915175203597455534847552400816280225290190894019795356708080578 | None | ||
| chip_sw_clkmgr_jitter_reduced_freq | 58292104857811762050544695539258302668787626319923161251708300538250213813767 | None | ||
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 82769662916518117847886799920809676723296386021824401780001893451764834162717 | None | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 82790398533616440430449458374958238835772559778254902915040724706487257873375 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 27761367802737688182660526406892953552478906152505846909428931165671202283911 | None | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 68944270945762244610343295230086347763018880957294750352128063901257557397787 | None | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 62179188079279802698875891049221863344642831140443864738968758052975190272855 | None | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 6066476464541913162739229072173521401126021676138045037624597400527509450744 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 47409471670476066464465531928117760134062498543121129979973744674610112967506 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 17291410654105303430436586978977252992503319304240139352169156583847653314451 | None | ||
| chip_sw_flash_init_reduced_freq | 74542202375333542128770888003406738819416471981899030233996852116465798209419 | None | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 27917514576571559641274439816599209991901862491126873252926767938152773335149 | None | ||
| chip_sw_power_idle_load | 91160068821929190432329499725434591081007661466073589508737419752310337362128 | None | ||
| chip_sw_power_sleep_load | 103392774524514863385633347884041730564769947768573921122512751529612822485314 | None | ||
| chip_sw_ast_clk_rst_inputs | 554925057081852061471070174009013298573820958794350184646720195175963999851 | None | ||
| chip_sw_power_virus | 39087184964475914503037557260437937867933795766906347106872593700468582746880 | None | ||
| chip_sw_flash_scrambling_smoketest | 93608739293419687380650980964268510377471697799484473275809291610762472980682 | None | ||
| chip_sw_flash_ctrl_mem_protection | 12700154155460484299723627499853775783395046118259753707376815489597581894761 | None | ||
| ate_bootstrap_flash_erase | 7794309738512428951162798294792223958870874401843944647308855982922920805242 | None | ||
| ate_bootstrap_one_frame | 66604741903222052672526058606732919886256870527258770429900894514047261800755 | None | ||
| ate_bootstrap_disjoint | 92120280475760029907301497591705749790704247171187317212063992625821320912908 | None | ||
| rom_e2e_smoke | 10722041062186627492800516203089864836162744620177323899805628264414616715412 | None | ||
| rom_e2e_shutdown_exception_c | 16472822005575041359011768246572945945478112953839042486351855187691164303986 | None | ||
| rom_e2e_shutdown_output | 112436644168007259940808569499150004505420820516420772066389702639788464653490 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 8193478009904813400951461406982611800828533276995399219757692923798676656877 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 65707612719823947821950755852878793437958449563883539825443724025731319348090 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 28349470634125394641211303056123416168048863753832761855128706810461602975996 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 26701477820879382005893491709957217590678385385004295715483228325512108122329 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 42809355010841355515994034481562190371879028598031968982987874969582349687428 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 42531760879417682316566103041454989710668445285878589177480802963339945614242 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 80046482517023874239303010305915265609635757060929750579682619789355014426398 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 29903459273757015892164307208643702548721328271545968275944101353005753525366 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 78720328954840444187710053096266599732496960268136497698102637855431419178171 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 6252720950536870532341545661947004058942480798153420560278200672592626522169 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 94946006255534274346628005666723446958742334368961721835143411653474332306808 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 68639501786810275411844853905275100278842393872048294467109620388796679211461 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 95783620388294627714328152246388944642623262488885268362418726295985350595553 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 89790563588443119728224723060486012885354422366567001421120471272656740736718 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 103709440975396653522083272154900222522180744315462262393844817019753304891288 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 94141996179520085878227443948333426538063398506653647117499332160671926287370 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 82538821489045135549489326079502565969539161724631193097587179311666377783013 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 9406308602722214559790921732296926479131628621586421080830205042354604600784 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 36078720606386341848624175182561159256170962644282779761518110396690397466797 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 35291479619242702335104978414814359023601209190571700939657644853269012939385 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 109034910084249761846972962187681362665302499006492405502788369833958065646593 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 91768426410886007782923110356274322570835242525088760345517826325838220376780 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 75958974428779690251547618119653001335397304363612500327446557993756253585962 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 79927449819899524138754809749381975556447977519368174679910728198103091341500 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 48684953604842646074509158967676883076669262248688996629370640041674334950078 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 25736369055368909750053375078658038971434027990597983271687102379671111541142 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 17288449046146157311512947361680865842902948553697445085784655866632425929866 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 6447283613888812698312837050164286580298523583914214582844237914802937437835 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 29352348397089902678479824398000142375970879021666550254609479558227249653890 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 100259525412244505762365437873348649873280107720083639886204155095900244315541 | None | ||
| rom_e2e_asm_init_test_unlocked0 | 58645783086835954453905403804629940295202291175290913022281569149200464234030 | None | ||
| rom_e2e_asm_init_dev | 13639013135583963902295053079009806239838307531279151959655868287484853395222 | None | ||
| rom_e2e_asm_init_prod | 76694501535420158699670502248791698575161555666319232253493820712982425697827 | None | ||
| rom_e2e_asm_init_prod_end | 76239942482520907178996883533218599307467081032242735428279376813823385333248 | None | ||
| rom_e2e_asm_init_rma | 39231342642546346116461568452266472110409402333976264048740619476553632723694 | None | ||
| rom_e2e_jtag_debug_test_unlocked0 | 54459010405564318672586785234935284238902751079718615733962482758562368473055 | None | ||
| rom_e2e_jtag_debug_dev | 113726836415766042120190468921433594507388774330561737351404539226203163976025 | None | ||
| rom_e2e_jtag_debug_rma | 83247081442274212062507676977214544430709419090352660648709941752763210717459 | None | ||
| rom_e2e_jtag_inject_test_unlocked0 | 58137704010825544478631264916023961486142946179769851095050227337230679891519 | None | ||
| rom_e2e_jtag_inject_dev | 45715108707765051884620868948754839821217247086860235366212026177495056182290 | None | ||
| rom_e2e_jtag_inject_rma | 69448993429093260508321020977043053050487281886819799113199103228066693937031 | None | ||
| rom_e2e_static_critical | 17547433871843268605853080829823439609100259212720835964449031096005646478288 | None | ||
| rom_e2e_keymgr_init_rom_ext_meas | 42792748121251911689756513183279688989142826222004098087353655644404796067582 | None | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 68817341037446803783604198904881862082894344744272553766238810053100207858051 | None | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 20283549238162738921674175567695174835497302668453358515954174182868989627276 | None | ||
| rom_volatile_raw_unlock | 4424206863969790963421763745601483642545649447605123821317732832594331469589 | None | ||
| rom_raw_unlock | 73747514318755920868872453381650832678024939618648083201470126007419272179906 | None | ||
| rom_e2e_self_hash | 45856228825068924869094603199122812500754854588956626867460192103091011670771 | None | ||
| rom_keymgr_functest | 45147417273256202253112982876309942872352552262253045569087737367803684855918 | None | ||
| chip_sw_aes_smoketest | 100865071876741862635126935174419391971429981318858999267191561191065614345419 | None | ||
| chip_sw_aon_timer_smoketest | 54163221672133775850347567136769714290623420620518649485814214087760968058303 | None | ||
| chip_sw_clkmgr_smoketest | 99953986439380772118982596629814893139547927808356895153360410259337015438850 | None | ||
| chip_sw_csrng_smoketest | 69351446351823449962789673781087105443831946513071749355663660317816198939768 | None | ||
| chip_sw_entropy_src_smoketest | 82573493535591920009049301626144954045851544274930904737142141257684367903700 | None | ||
| chip_sw_gpio_smoketest | 82859643208453268371886127302032560668774521162521516286671371196540710381831 | None | ||
| chip_sw_hmac_smoketest | 64504591145423414473649996688135872405143506641561267426784184916322581510129 | None | ||
| chip_sw_kmac_smoketest | 91583825719161999619080606556460522828484267882155693261523133123447759323142 | None | ||
| chip_sw_otbn_smoketest | 58188250457832287512219056098016609490278514347940145539317731458782576011472 | None | ||
| chip_sw_otp_ctrl_smoketest | 94581726309184712177305753268029743182586590572448583821299031554877806314990 | None | ||
| chip_sw_pwrmgr_smoketest | 62311319612667595522241664480111246484930035382068365161330201647964868577298 | None | ||
| chip_sw_pwrmgr_usbdev_smoketest | 32209607712036423684435982367381370636864630682386898440148313513765090069978 | None | ||
| chip_sw_rv_plic_smoketest | 58511681893086272049751528085599342747147185701927178057869975718168486159104 | None | ||
| chip_sw_rv_timer_smoketest | 42064395450661810439649405056158046609065578740575583864232118440033907310638 | None | ||
| chip_sw_rstmgr_smoketest | 106672399153690695350803052661137213911275535201265420888811036590716983165395 | None | ||
| chip_sw_sram_ctrl_smoketest | 90478212088164334469669454213256660266327422526572305294340965698644302863271 | None | ||
| chip_sw_uart_smoketest | 6801166899557923725720498373119088950206098416558196716420120130099926906255 | None | ||
| xbar_smoke | 90009419334659351217971660382288550275572586919006480236061089871788092380073 | None | ||
| xbar_smoke_zero_delays | 4834873613301639748331415452492936488488981467857709568947850085271352318513 | None | ||
| xbar_smoke_large_delays | 109398341653378813947594896307345950873034874418811117384517076288801445712325 | None | ||
| xbar_smoke_slow_rsp | 26097396221160828612750720044517205171473993163919500842432335664608098033565 | None | ||
| xbar_random | 89331393714994499586474824599975569308972420912050426881975948240798397812973 | None | ||
| xbar_random_zero_delays | 21051535120412892885217780668793251770761136372815152432198857990836133622687 | None | ||
| xbar_random_large_delays | 30397340993778319281489705321361154267401801902034417785055251268811838341444 | None | ||
| xbar_random_slow_rsp | 77685316003844735958414891315802866183162179266643367940988041449905642724243 | None | ||
| xbar_access_same_device | 100579941501244977165498968212991752546102962730966372489653642503255575081769 | None | ||
| xbar_access_same_device_slow_rsp | 48301449580645867991886887269962491677827689541590569683605347010801909523796 | None | ||
| xbar_same_source | 87958313392993525976162340053852414577537497878653069714024071839202327155508 | None | ||
| xbar_error_random | 1538897148536243622140427833832970134906059647013522566159269015784041898245 | None | ||
| xbar_unmapped_addr | 106378214905018068292968123028440361068283955356753880601556764032405616161355 | None | ||
| xbar_error_and_unmapped_addr | 111062652412158692488673883934018446341598082548269145413170674906926961085783 | None | ||
| xbar_stress_all | 103350257238540564128226357254065737024015702337287415886197803256725804385589 | None | ||
| xbar_stress_all_with_rand_reset | 102165709051674933259606921670544360491754752426816908739087514590449846950565 | None | ||
| xbar_stress_all_with_error | 58326087264089493239612406975695427461338805738078461873496261357155250214304 | None | ||
| xbar_stress_all_with_reset_error | 32613451756042416056359452818414240896887650174294870556843516447718170064189 | None | ||
| chip_csr_hw_reset | 35119410831917304766469853673015221417712393596200031833217808056396435012570 | None | ||
| chip_csr_rw | 1725465563373330272954684383434294743972634515640846532834535973051605604420 | None | ||
| chip_csr_mem_rw_with_rand_reset | 32971473004273017879299964109278118540349157799873802051227381306352814157569 | None | ||
| chip | None | None | ||
| Error-[SE] Syntax error | 4 test runs | |||
| cover_reg_top | None | 3031 |
Following verilog source has syntax error :
Select on function call
"src/lowrisc_dv_rram_ctrl_bkdr_util_0.1/rram_ctrl_otp_bkdr_util.sv", 149:
token is ']'
|
|
| default | None | 3033 |
Following verilog source has syntax error :
Select on function call
"src/lowrisc_dv_rram_ctrl_bkdr_util_0.1/rram_ctrl_otp_bkdr_util.sv", 149:
token is ']'
|
|
| pad_ctrl_test_mode | None | 3031 |
Following verilog source has syntax error :
Select on function call
"src/lowrisc_dv_rram_ctrl_bkdr_util_0.1/rram_ctrl_otp_bkdr_util.sv", 149:
token is ']'
|
|
| xbar_build_mode | None | 3033 |
Following verilog source has syntax error :
Select on function call
"src/lowrisc_dv_rram_ctrl_bkdr_util_0.1/rram_ctrl_otp_bkdr_util.sv", 149:
token is ']'
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| chip | None | None | ||