Simulation Results: clkmgr

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.19 %
  • code
  • 98.21 %
  • assert
  • 95.76 %
  • func
  • 85.59 %
  • line
  • 98.95 %
  • branch
  • 98.48 %
  • cond
  • 94.44 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.860s 26.160us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 33.117us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.770s 46.971us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.740s 1143.490us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.490s 205.643us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.070s 43.379us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.770s 46.971us 1 1 100.00
clkmgr_csr_aliasing 1.490s 205.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.850s 14.877us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.840s 29.254us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.840s 30.644us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.960s 71.883us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.860s 26.160us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 4.730s 1409.043us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.090s 868.699us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 4.730s 1409.043us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 27.600s 9070.756us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.730s 42.129us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.440s 516.553us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.440s 516.553us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 33.117us 1 1 100.00
clkmgr_csr_rw 0.770s 46.971us 1 1 100.00
clkmgr_csr_aliasing 1.490s 205.643us 1 1 100.00
clkmgr_same_csr_outstanding 1.020s 39.661us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 33.117us 1 1 100.00
clkmgr_csr_rw 0.770s 46.971us 1 1 100.00
clkmgr_csr_aliasing 1.490s 205.643us 1 1 100.00
clkmgr_same_csr_outstanding 1.020s 39.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.940s 13.795us 0 1 0.00
clkmgr_tl_intg_err 39.480s 10073.122us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 134.961us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 134.961us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 134.961us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 134.961us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.360s 187.928us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 39.480s 10073.122us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 4.730s 1409.043us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.090s 868.699us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 134.961us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.800s 33.936us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.910s 100.538us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.800s 24.124us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.800s 24.549us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.650s 17.123us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.770s 46.971us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.940s 13.795us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 46.971us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 46.971us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.940s 13.795us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.790s 1827.218us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 46.800s 10394.743us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 8257180139228193584961010244845663242979944135256904340940959984255123947601 93
UVM_INFO @ 13795465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 16148109757502680792912115137157414750416431365591193100574969041716278495126 179
UVM_INFO @ 10073121764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---