Simulation Results: edn/edn0

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.27 %
  • code
  • 78.62 %
  • assert
  • 95.23 %
  • func
  • 78.97 %
  • line
  • 96.79 %
  • branch
  • 88.56 %
  • cond
  • 83.75 %
  • toggle
  • 72.41 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 62.159us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.800s 138.375us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 21.652us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 166.386us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.230s 37.756us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.200s 91.637us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 21.652us 1 1 100.00
edn_csr_aliasing 1.230s 37.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.240s 51.897us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.240s 51.897us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.240s 51.897us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.960s 26.227us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 112.099us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 25.717us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 32.533us 1 1 100.00
edn_disable_auto_req_mode 1.040s 188.972us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.220s 178.240us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.820s 29.262us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.250s 61.235us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.110s 132.604us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.110s 132.604us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.800s 138.375us 1 1 100.00
edn_csr_rw 0.780s 21.652us 1 1 100.00
edn_csr_aliasing 1.230s 37.756us 1 1 100.00
edn_same_csr_outstanding 1.200s 70.694us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.800s 138.375us 1 1 100.00
edn_csr_rw 0.780s 21.652us 1 1 100.00
edn_csr_aliasing 1.230s 37.756us 1 1 100.00
edn_same_csr_outstanding 1.200s 70.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.150s 1424.116us 1 1 100.00
edn_tl_intg_err 1.410s 62.354us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.960s 21.665us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 112.099us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.150s 1424.116us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.150s 1424.116us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.150s 1424.116us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.150s 1424.116us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 112.099us 1 1 100.00
edn_sec_cm 7.150s 1424.116us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 112.099us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.410s 62.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 33.570s 8258.361us 1 1 100.00