Simulation Results: flash_ctrl

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.44 %
  • code
  • 93.63 %
  • assert
  • 97.02 %
  • func
  • 95.67 %
  • line
  • 95.97 %
  • branch
  • 97.23 %
  • cond
  • 93.64 %
  • toggle
  • 95.60 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
96.55%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 56.800s 52.060us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.540s 22.907us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.920s 163.827us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.410s 68.474us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 23.930s 481.121us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 27.130s 854.322us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 6.940s 143.715us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.410s 68.474us 1 1 100.00
flash_ctrl_csr_aliasing 27.130s 854.322us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.860s 17.314us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 9.390s 19.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.420s 79.902us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 29.080s 47.853us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1070.210s 342613.528us 1 1 100.00
flash_ctrl_hw_rma_reset 500.040s 40129.338us 1 1 100.00
flash_ctrl_lcmgr_intg 5.870s 41.833us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 939.710s 478341.291us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 155.120s 2812.778us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.870s 69.486us 1 1 100.00
full_memory_access 0 1 0.00
flash_ctrl_full_mem_access 1377.760s 373456.070us 0 1 0.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 44.550s 60.305us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.370s 219.014us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.530s 65.782us 1 1 100.00
flash_ctrl_re_evict 20.670s 250.847us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 55.000s 234.148us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 55.000s 234.148us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 222.000s 10415.973us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 17.780s 1173.047us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 70.750s 36.595us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 364.630s 3050.603us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 333.810s 917.569us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1030.350s 1241.559us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.570s 24.436us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 91.230s 1477.910us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.830s 37.129us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.100s 53.807us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 48.420s 134.417us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 16.230s 1534.473us 1 1 100.00
flash_ctrl_otp_reset 59.770s 60.455us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1070.210s 342613.528us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 119.170s 1747.314us 1 1 100.00
flash_ctrl_intr_wr 54.260s 3470.723us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 67.550s 7704.675us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 86.930s 37875.362us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 37.960s 2129.102us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.800s 980.122us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.990s 31.160us 1 1 100.00
flash_ctrl_ro_derr 85.320s 1617.975us 1 1 100.00
flash_ctrl_rw_derr 112.470s 2639.449us 1 1 100.00
flash_ctrl_derr_detect 89.790s 629.570us 1 1 100.00
flash_ctrl_integrity 337.440s 4665.066us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.180s 57.015us 1 1 100.00
flash_ctrl_ro_serr 75.900s 969.851us 1 1 100.00
flash_ctrl_rw_serr 127.870s 2380.831us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 42.060s 4715.464us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 50.880s 11078.992us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 92.070s 10712.573us 1 1 100.00
flash_ctrl_write_word_sweep 8.880s 292.924us 1 1 100.00
flash_ctrl_read_word_sweep 11.870s 57.131us 1 1 100.00
flash_ctrl_ro 73.580s 3330.964us 1 1 100.00
flash_ctrl_rw 3602.639s 0.000us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 19.440s 1478.994us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 544.870s 42239.711us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 185.640s 10018.968us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.090s 37.213us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.790s 56.938us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.940s 196.153us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.940s 196.153us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.920s 163.827us 1 1 100.00
flash_ctrl_csr_rw 8.410s 68.474us 1 1 100.00
flash_ctrl_csr_aliasing 27.130s 854.322us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.770s 88.266us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.920s 163.827us 1 1 100.00
flash_ctrl_csr_rw 8.410s 68.474us 1 1 100.00
flash_ctrl_csr_aliasing 27.130s 854.322us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.770s 88.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 30.620s 176.249us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 30.620s 176.249us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 30.620s 176.249us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 30.620s 176.249us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 36.300s 1059.226us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1603.430s 2430.469us 1 1 100.00
flash_ctrl_tl_intg_err 301.430s 6091.055us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 301.430s 6091.055us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 301.430s 6091.055us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.090s 76.655us 1 1 100.00
flash_ctrl_wr_intg 6.910s 52.550us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 56.800s 52.060us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 59.770s 60.455us 1 1 100.00
flash_ctrl_disable 10.830s 37.129us 1 1 100.00
flash_ctrl_sec_info_access 46.790s 14842.656us 1 1 100.00
flash_ctrl_connect 8.100s 53.807us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.090s 31.822us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.410s 68.474us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.620s 176.249us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.410s 68.474us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.620s 176.249us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.410s 68.474us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.620s 176.249us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.830s 37.129us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.090s 76.655us 1 1 100.00
flash_ctrl_access_after_disable 6.260s 48.226us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.820s 67.460us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.830s 37.129us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 17.780s 1173.047us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 3602.639s 0.000us 0 1 0.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 127.870s 2380.831us 1 1 100.00
flash_ctrl_rw_derr 112.470s 2639.449us 1 1 100.00
flash_ctrl_integrity 337.440s 4665.066us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1070.210s 342613.528us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1603.430s 2430.469us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1603.430s 2430.469us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1603.430s 2430.469us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1603.430s 2430.469us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.450s 743.777us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.560s 22.522us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.300s 41.978us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1603.430s 2430.469us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1603.430s 2430.469us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1603.430s 2430.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 23.580s 243.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 281.910s 964.059us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (flash_ctrl_scoreboard.sv:735) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * 1 test run
flash_ctrl_full_mem_access 7628446339298098073927666166869579262377266301349164052078041116130531006415 275581
UVM_INFO @ 373456070.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
flash_ctrl_rw 5612969589526717331166335791485221642754210030422149950597523230495166684810 None