Simulation Results: hmac

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.31 %
  • code
  • 97.65 %
  • assert
  • 97.38 %
  • func
  • 42.89 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.67 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.230s 658.009us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.820s 33.879us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.680s 18.999us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.550s 8125.414us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.310s 667.456us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.250s 41.039us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.680s 18.999us 1 1 100.00
hmac_csr_aliasing 4.310s 667.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 18.210s 629.816us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 24.890s 1400.580us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.830s 1546.689us 1 1 100.00
hmac_test_sha384_vectors 335.720s 137766.553us 1 1 100.00
hmac_test_sha512_vectors 20.300s 730.609us 1 1 100.00
hmac_test_hmac256_vectors 9.800s 6894.528us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 676.493us 1 1 100.00
hmac_test_hmac512_vectors 8.410s 312.803us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.280s 2028.394us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 17.800s 2146.407us 1 1 100.00
error 1 1 100.00
hmac_error 37.950s 7788.135us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 30.990s 15068.791us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.230s 658.009us 1 1 100.00
hmac_long_msg 18.210s 629.816us 1 1 100.00
hmac_back_pressure 24.890s 1400.580us 1 1 100.00
hmac_datapath_stress 17.800s 2146.407us 1 1 100.00
hmac_burst_wr 8.280s 2028.394us 1 1 100.00
hmac_stress_all 215.450s 88591.393us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.230s 658.009us 1 1 100.00
hmac_long_msg 18.210s 629.816us 1 1 100.00
hmac_back_pressure 24.890s 1400.580us 1 1 100.00
hmac_datapath_stress 17.800s 2146.407us 1 1 100.00
hmac_wipe_secret 30.990s 15068.791us 1 1 100.00
hmac_test_sha256_vectors 8.830s 1546.689us 1 1 100.00
hmac_test_sha384_vectors 335.720s 137766.553us 1 1 100.00
hmac_test_sha512_vectors 20.300s 730.609us 1 1 100.00
hmac_test_hmac256_vectors 9.800s 6894.528us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 676.493us 1 1 100.00
hmac_test_hmac512_vectors 8.410s 312.803us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.230s 658.009us 1 1 100.00
hmac_long_msg 18.210s 629.816us 1 1 100.00
hmac_back_pressure 24.890s 1400.580us 1 1 100.00
hmac_datapath_stress 17.800s 2146.407us 1 1 100.00
hmac_burst_wr 8.280s 2028.394us 1 1 100.00
hmac_error 37.950s 7788.135us 1 1 100.00
hmac_wipe_secret 30.990s 15068.791us 1 1 100.00
hmac_test_sha256_vectors 8.830s 1546.689us 1 1 100.00
hmac_test_sha384_vectors 335.720s 137766.553us 1 1 100.00
hmac_test_sha512_vectors 20.300s 730.609us 1 1 100.00
hmac_test_hmac256_vectors 9.800s 6894.528us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 676.493us 1 1 100.00
hmac_test_hmac512_vectors 8.410s 312.803us 1 1 100.00
hmac_stress_all 215.450s 88591.393us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 215.450s 88591.393us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.660s 25.560us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.640s 100.440us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.200s 48.916us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.200s 48.916us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.820s 33.879us 1 1 100.00
hmac_csr_rw 0.680s 18.999us 1 1 100.00
hmac_csr_aliasing 4.310s 667.456us 1 1 100.00
hmac_same_csr_outstanding 1.080s 227.317us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.820s 33.879us 1 1 100.00
hmac_csr_rw 0.680s 18.999us 1 1 100.00
hmac_csr_aliasing 4.310s 667.456us 1 1 100.00
hmac_same_csr_outstanding 1.080s 227.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.830s 89.638us 1 1 100.00
hmac_tl_intg_err 2.680s 171.749us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.680s 171.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.230s 658.009us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.320s 156.254us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 78.720s 11321.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.320s 665.753us 1 1 100.00