Simulation Results: i2c

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.24 %
  • code
  • 78.99 %
  • assert
  • 97.46 %
  • func
  • 79.28 %
  • line
  • 96.47 %
  • branch
  • 92.55 %
  • cond
  • 86.06 %
  • toggle
  • 74.04 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
95.12%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 15.290s 2532.737us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 13.220s 761.658us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.870s 71.239us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.890s 26.573us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.870s 2567.027us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.360s 120.668us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.020s 46.414us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.890s 26.573us 1 1 100.00
i2c_csr_aliasing 1.360s 120.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 1.210s 75.623us 1 1 100.00
host_stress_all 0 1 0.00
i2c_host_stress_all 465.660s 132165.979us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 24.430s 50186.378us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.680s 17.857us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 80.910s 79489.351us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 21.800s 2845.626us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.880s 753.415us 1 1 100.00
i2c_host_fifo_fmt_empty 12.380s 1822.471us 1 1 100.00
i2c_host_fifo_reset_rx 4.860s 2136.827us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 26.670s 2212.793us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.680s 1440.520us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.490s 365.731us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.530s 1540.226us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 121.730s 73911.738us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.840s 1537.447us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 24.280s 1728.140us 1 1 100.00
i2c_target_intr_smoke 2.710s 2204.735us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.150s 517.721us 1 1 100.00
i2c_target_fifo_reset_tx 0.920s 162.690us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 23.910s 26476.978us 1 1 100.00
i2c_target_stress_rd 24.280s 1728.140us 1 1 100.00
i2c_target_intr_stress_wr 12.500s 10976.112us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.360s 3392.818us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 31.530s 3098.605us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.130s 2173.615us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.700s 301.779us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.470s 1240.175us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.740s 238.877us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 24.430s 50186.378us 1 1 100.00
i2c_host_perf_precise 1.140s 179.253us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.680s 1440.520us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.110s 56.501us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.800s 1093.175us 1 1 100.00
i2c_target_nack_acqfull_addr 2.290s 7760.427us 1 1 100.00
i2c_target_nack_txstretch 1.380s 133.661us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.410s 812.343us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.430s 444.805us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.790s 80.362us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.680s 46.527us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.670s 270.426us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.670s 270.426us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.870s 71.239us 1 1 100.00
i2c_csr_rw 0.890s 26.573us 1 1 100.00
i2c_csr_aliasing 1.360s 120.668us 1 1 100.00
i2c_same_csr_outstanding 0.970s 47.666us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.870s 71.239us 1 1 100.00
i2c_csr_rw 0.890s 26.573us 1 1 100.00
i2c_csr_aliasing 1.360s 120.668us 1 1 100.00
i2c_same_csr_outstanding 0.970s 47.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.180s 138.239us 1 1 100.00
i2c_sec_cm 0.850s 44.697us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.180s 138.239us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 29.080s 839.177us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.880s 61.959us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 15.110s 9695.896us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 32651587156097205483285431960063819783681063351792562985944385287352192660247 105
UVM_INFO @ 839177452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 107132158471821589771829666743832167932155166446483033277520611540356754489967 110
UVM_INFO @ 9695895735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 1 test run
i2c_host_stress_all 60474333739332074630390387826195853621094336841337813617015921959457524699230 154
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5406714
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 57946979622945114775428150280398680719077642447689685600739503979606305702859 90
UVM_INFO @ 1540225632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 21450457835798673934210376882707528189702433972382068863897008419857577068158 84
UVM_INFO @ 61959343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---