Simulation Results: lc_ctrl/volatile_unlock_disabled

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.67 %
  • code
  • 83.99 %
  • assert
  • 94.83 %
  • func
  • 93.19 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.08 %
  • toggle
  • 86.44 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.630s 133.674us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 47.478us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 51.576us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.070s 235.690us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 90.669us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.940s 90.350us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 51.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 90.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.890s 402.119us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.320s 323.234us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.700s 17.195us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.640s 68.099us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.590s 2037.977us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_prog_failure 1.640s 68.099us 1 1 100.00
lc_ctrl_errors 6.590s 2037.977us 1 1 100.00
lc_ctrl_security_escalation 4.460s 431.811us 1 1 100.00
lc_ctrl_jtag_state_failure 21.920s 8070.265us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.530s 372.128us 1 1 100.00
lc_ctrl_jtag_errors 24.340s 6264.431us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.340s 1334.869us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.160s 1102.216us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.530s 372.128us 1 1 100.00
lc_ctrl_jtag_errors 24.340s 6264.431us 1 1 100.00
lc_ctrl_jtag_access 4.750s 636.027us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.760s 3898.324us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.530s 112.018us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.010s 52.507us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.630s 16291.075us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.610s 546.874us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.090s 75.655us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.350s 77.709us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 104.909us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.470s 444.901us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 45.928us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 242.920s 33134.126us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.820s 48.243us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.560s 143.364us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.560s 143.364us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 47.478us 1 1 100.00
lc_ctrl_csr_rw 0.830s 51.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 90.669us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.130s 33.430us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 47.478us 1 1 100.00
lc_ctrl_csr_rw 0.830s 51.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 90.669us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.130s 33.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
lc_ctrl_tl_intg_err 1.280s 54.451us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.280s 54.451us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.320s 323.234us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.770s 796.205us 1 1 100.00
lc_ctrl_sec_cm 6.480s 1270.528us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.460s 431.811us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.890s 402.119us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.160s 1102.216us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.490s 274.723us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.490s 274.723us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.200s 417.151us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.940s 1416.740us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.940s 1416.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 18.700s 3707.131us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 85342182348618881351125182477904941631854123059367869895606513252095547020579 1061
UVM_INFO @ 3707131005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---