Simulation Results: lc_ctrl/volatile_unlock_enabled

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.68 %
  • code
  • 84.39 %
  • assert
  • 94.83 %
  • func
  • 92.83 %
  • line
  • 97.26 %
  • branch
  • 93.80 %
  • cond
  • 79.41 %
  • toggle
  • 86.99 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.320s 285.350us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 48.835us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.790s 30.726us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.980s 94.115us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 25.155us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.530s 310.706us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.790s 30.726us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 25.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.520s 181.661us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.550s 1257.542us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.860s 40.439us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.390s 139.732us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.910s 239.215us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_prog_failure 1.390s 139.732us 1 1 100.00
lc_ctrl_errors 3.910s 239.215us 1 1 100.00
lc_ctrl_security_escalation 5.350s 638.012us 1 1 100.00
lc_ctrl_jtag_state_failure 22.890s 25905.607us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.690s 273.800us 1 1 100.00
lc_ctrl_jtag_errors 28.930s 17719.881us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.920s 455.082us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.910s 334.732us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.690s 273.800us 1 1 100.00
lc_ctrl_jtag_errors 28.930s 17719.881us 1 1 100.00
lc_ctrl_jtag_access 3.910s 4516.437us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.770s 3254.273us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.330s 335.087us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.900s 46.922us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.310s 2344.218us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.870s 186.505us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.060s 75.424us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.440s 87.001us 1 1 100.00
lc_ctrl_jtag_alert_test 0.850s 35.679us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.840s 361.538us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.720s 14.771us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 15.940s 1317.799us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.980s 21.765us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.450s 44.563us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.450s 44.563us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 48.835us 1 1 100.00
lc_ctrl_csr_rw 0.790s 30.726us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 25.155us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.030s 29.111us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 48.835us 1 1 100.00
lc_ctrl_csr_rw 0.790s 30.726us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 25.155us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.030s 29.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
lc_ctrl_tl_intg_err 1.240s 499.085us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.240s 499.085us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.550s 1257.542us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.390s 3832.735us 1 1 100.00
lc_ctrl_sec_cm 6.410s 1091.928us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.350s 638.012us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.520s 181.661us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.910s 334.732us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.660s 472.227us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.660s 472.227us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.790s 988.494us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.740s 288.261us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.740s 288.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 23.320s 8641.338us 1 1 100.00