Simulation Results: otbn

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.87 %
  • code
  • 81.39 %
  • assert
  • 89.49 %
  • func
  • 98.73 %
  • block
  • 97.73 %
  • line
  • 97.93 %
  • branch
  • 81.85 %
  • toggle
  • 79.56 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
85.71%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 72.494us 1 1 100.00
otbn_smoke_vectorized 7.000s 70.920us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 14.715us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 48.976us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 110.033us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 53.035us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 4.000s 45.605us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 48.976us 1 1 100.00
otbn_csr_aliasing 3.000s 53.035us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 86.000s 1487.115us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 21.000s 2351.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 21.000s 157.925us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 37.000s 144.945us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 69.000s 483.808us 1 1 100.00
stress_all 0 1 0.00
otbn_stress_all 89.547s 0.000us 0 1 0.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 52.761us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 9.000s 64.376us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 15.526us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 17.497us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 18.735us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 483.671us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 483.671us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 14.715us 1 1 100.00
otbn_csr_rw 3.000s 48.976us 1 1 100.00
otbn_csr_aliasing 3.000s 53.035us 1 1 100.00
otbn_same_csr_outstanding 4.000s 125.993us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 14.715us 1 1 100.00
otbn_csr_rw 3.000s 48.976us 1 1 100.00
otbn_csr_aliasing 3.000s 53.035us 1 1 100.00
otbn_same_csr_outstanding 4.000s 125.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 219.638us 1 1 100.00
otbn_dmem_err 7.000s 29.212us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 6.000s 41.504us 1 1 100.00
otbn_controller_ispr_rdata_err 6.000s 42.292us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 213.394us 1 1 100.00
otbn_urnd_err 5.000s 10.918us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 25.618us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 9.000s 140.477us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 15.778us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
otbn_tl_intg_err 16.000s 903.499us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 86.000s 488.413us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 72.494us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 29.212us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 219.638us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 903.499us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 52.761us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 219.638us 1 1 100.00
otbn_dmem_err 7.000s 29.212us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 64.376us 1 1 100.00
otbn_illegal_mem_acc 6.000s 25.618us 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 219.638us 1 1 100.00
otbn_dmem_err 7.000s 29.212us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 64.376us 1 1 100.00
otbn_illegal_mem_acc 6.000s 25.618us 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 52.761us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 219.638us 1 1 100.00
otbn_dmem_err 7.000s 29.212us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 64.376us 1 1 100.00
otbn_illegal_mem_acc 6.000s 25.618us 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 14.079us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 22.341us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 42.000s 771.349us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 42.000s 771.349us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 25.191us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 266.880us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 19.906us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 19.906us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 13.000s 27.651us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 69.000s 483.808us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 10.000s 36.358us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 42.378us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 330.000s 7112.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 183.000s 3364.749us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 53737147161426896672231117333386807612523895487274298309763736197355044890603 328
UVM_INFO @ 144944638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_stress_all 59280360187808235689399338348092904217208833155369310373133412639756812015292 None
<builtin>: in <toplevel>
Repository rule http_archive defined at:
/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:444:31: in <toplevel>
ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:159:45: An error occurred during the fetch of repository 'lowrisc_misc_linters+':
Traceback (most recent call last):
File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 159, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp15268901694719729804/20250217_01.tar.gz: GET returned 429 Too Many Requests
ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp15268901694719729804/20250217_01.tar.gz: GET returned 429 Too Many Requests
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 37
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 618117099485325374727480413102291482381058897939431186828058154051023734259 263
UVM_INFO @ 3364748808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---