| V1 |
|
88.89% |
| V2 |
|
95.00% |
| V2S |
|
88.89% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| otp_ctrl_wake_up | 1.790s | 104.100us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 11.030s | 10503.140us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 1.550s | 67.331us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_rw | 1.170s | 40.080us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_bit_bash | 4.400s | 750.425us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_aliasing | 4.420s | 377.158us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 1.040s | 53.188us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otp_ctrl_csr_rw | 1.170s | 40.080us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 4.420s | 377.158us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otp_ctrl_mem_walk | 1.150s | 131.879us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otp_ctrl_mem_partial_access | 1.260s | 139.231us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 1 | 1 | 100.00 | |||
| otp_ctrl_partition_walk | 14.240s | 3260.226us | 1 | 1 | 100.00 | |
| init_fail | 1 | 1 | 100.00 | |||
| otp_ctrl_init_fail | 2.850s | 169.008us | 1 | 1 | 100.00 | |
| partition_check | 1 | 2 | 50.00 | |||
| otp_ctrl_background_chks | 17.760s | 1905.156us | 1 | 1 | 100.00 | |
| otp_ctrl_check_fail | 1.250s | 77.885us | 0 | 1 | 0.00 | |
| regwen_during_otp_init | 1 | 1 | 100.00 | |||
| otp_ctrl_regwen | 5.900s | 1006.775us | 1 | 1 | 100.00 | |
| partition_lock | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 10.960s | 486.592us | 1 | 1 | 100.00 | |
| interface_key_check | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_key_req | 14.480s | 1073.963us | 1 | 1 | 100.00 | |
| lc_interactions | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_req | 3.630s | 323.588us | 1 | 1 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| otp_dai_errors | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_errs | 6.370s | 1589.437us | 1 | 1 | 100.00 | |
| otp_macro_errors | 1 | 1 | 100.00 | |||
| otp_ctrl_macro_errs | 16.150s | 2174.490us | 1 | 1 | 100.00 | |
| test_access | 1 | 1 | 100.00 | |||
| otp_ctrl_test_access | 10.380s | 10471.059us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otp_ctrl_stress_all | 33.450s | 25213.586us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otp_ctrl_intr_test | 1.190s | 84.233us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otp_ctrl_alert_test | 1.400s | 63.157us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_errors | 2.080s | 206.180us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_errors | 2.080s | 206.180us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 1.550s | 67.331us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.170s | 40.080us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 4.420s | 377.158us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 1.920s | 81.348us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 1.550s | 67.331us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.170s | 40.080us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 4.420s | 377.158us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 1.920s | 81.348us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| otp_ctrl_tl_intg_err | 7.010s | 9889.626us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_intg_err | 7.010s | 9889.626us | 1 | 1 | 100.00 | |
| sec_cm_secret_mem_scramble | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 11.030s | 10503.140us | 1 | 1 | 100.00 | |
| sec_cm_part_mem_digest | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 11.030s | 10503.140us | 1 | 1 | 100.00 | |
| sec_cm_dai_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_kdi_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_lci_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_part_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_scrmbl_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_dai_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_kdi_seed_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_kdi_entropy_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_lci_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_part_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_scrmbl_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_timer_integ_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_timer_cnsty_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_timer_lfsr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_dai_fsm_local_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_lci_fsm_local_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| sec_cm_kdi_fsm_local_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| sec_cm_part_fsm_local_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| otp_ctrl_macro_errs | 16.150s | 2174.490us | 1 | 1 | 100.00 | |
| sec_cm_scrmbl_fsm_local_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| sec_cm_timer_fsm_local_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_dai_fsm_global_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_lci_fsm_global_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| sec_cm_kdi_fsm_global_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| sec_cm_part_fsm_global_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| otp_ctrl_macro_errs | 16.150s | 2174.490us | 1 | 1 | 100.00 | |
| sec_cm_scrmbl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| sec_cm_timer_fsm_global_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 3.750s | 957.054us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_part_data_reg_integrity | 1 | 1 | 100.00 | |||
| otp_ctrl_init_fail | 2.850s | 169.008us | 1 | 1 | 100.00 | |
| sec_cm_part_data_reg_bkgn_chk | 0 | 1 | 0.00 | |||
| otp_ctrl_check_fail | 1.250s | 77.885us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_regren | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 10.960s | 486.592us | 1 | 1 | 100.00 | |
| sec_cm_part_mem_sw_unreadable | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 10.960s | 486.592us | 1 | 1 | 100.00 | |
| sec_cm_part_mem_sw_unwritable | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 10.960s | 486.592us | 1 | 1 | 100.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 10.960s | 486.592us | 1 | 1 | 100.00 | |
| sec_cm_access_ctrl_mubi | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 10.960s | 486.592us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 11.030s | 10503.140us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 10.960s | 486.592us | 1 | 1 | 100.00 | |
| sec_cm_test_bus_lc_gated | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 11.030s | 10503.140us | 1 | 1 | 100.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 111.210s | 28816.050us | 1 | 1 | 100.00 | |
| sec_cm_direct_access_config_regwen | 1 | 1 | 100.00 | |||
| otp_ctrl_regwen | 5.900s | 1006.775us | 1 | 1 | 100.00 | |
| sec_cm_check_trigger_config_regwen | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 11.030s | 10503.140us | 1 | 1 | 100.00 | |
| sec_cm_check_config_regwen | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 11.030s | 10503.140us | 1 | 1 | 100.00 | |
| sec_cm_macro_mem_integrity | 1 | 1 | 100.00 | |||
| otp_ctrl_macro_errs | 16.150s | 2174.490us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 1 | 1 | 100.00 | |||
| otp_ctrl_low_freq_read | 14.890s | 9215.522us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 31.170s | 22808.415us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | 1 test run | |||
| otp_ctrl_check_fail | 72177261823099893433329565811095144540461292614275656116572267233086106572767 | 193 |
UVM_INFO @ 77884699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * | 1 test run | |||
| otp_ctrl_stress_all_with_rand_reset | 96714861973205565620938686669841533176962203612147121497110654626279631912337 | 9584 |
UVM_INFO @ 22808414562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:692) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | 1 test run | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 980561043055539330087270313800292267066712902269403078532210395322331866856 | 98 |
UVM_INFO @ 53188188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|