Simulation Results: pwrmgr

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.67 %
  • code
  • 97.40 %
  • assert
  • 97.91 %
  • func
  • 97.69 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.90 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 23.297us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.660s 57.674us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.790s 16.875us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.560s 756.933us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.800s 102.138us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.800s 50.284us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.790s 16.875us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 102.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.090s 225.806us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.090s 225.806us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.690s 26.086us 1 1 100.00
pwrmgr_lowpower_invalid 0.640s 93.048us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.660s 118.472us 1 1 100.00
pwrmgr_reset_invalid 0.830s 111.481us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.660s 118.472us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.130s 330.151us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.000s 299.680us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 1.080s 1000.000us 0 1 0.00
stress_all 0 1 0.00
pwrmgr_stress_all 12.870s 10039.130us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.650s 60.953us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.770s 1138.105us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.770s 1138.105us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 57.674us 1 1 100.00
pwrmgr_csr_rw 0.790s 16.875us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 102.138us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 43.575us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 57.674us 1 1 100.00
pwrmgr_csr_rw 0.790s 16.875us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 102.138us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 43.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.350s 442.923us 1 1 100.00
pwrmgr_sec_cm 1.070s 317.462us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.070s 317.462us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.070s 317.462us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.350s 442.923us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.910s 706.202us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.130s 330.151us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.790s 695.128us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.720s 108.555us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.700s 30.307us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.070s 317.462us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.070s 317.462us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.070s 317.462us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 46.225us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.610s 62.401us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.630s 27.838us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.790s 16.875us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.790s 16.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.770s 106.184us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.270s 684.077us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 92479473026272064740785570010235016013283125090932298068064172074557365425162 112
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 68157634570739571765716941943919624458090893967478152887506832117424854570690 187
UVM_INFO @ 10039130239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---