Simulation Results: rom_ctrl/32kb

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.87 %
  • code
  • 92.72 %
  • assert
  • 97.53 %
  • func
  • 97.35 %
  • line
  • 98.94 %
  • branch
  • 98.54 %
  • cond
  • 97.77 %
  • toggle
  • 95.02 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.030s 425.909us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.470s 68.820us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 1.760s 54.249us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.410s 121.630us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 1.770s 89.902us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.070s 61.673us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 1.760s 54.249us 1 1 100.00
rom_ctrl_csr_aliasing 1.770s 89.902us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.850s 55.585us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.950s 49.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 1.650s 9.404us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 6.550s 163.119us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.080s 393.598us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 1.840s 56.259us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.920s 212.593us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.920s 212.593us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.470s 68.820us 1 1 100.00
rom_ctrl_csr_rw 1.760s 54.249us 1 1 100.00
rom_ctrl_csr_aliasing 1.770s 89.902us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.210s 94.601us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.470s 68.820us 1 1 100.00
rom_ctrl_csr_rw 1.760s 54.249us 1 1 100.00
rom_ctrl_csr_aliasing 1.770s 89.902us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.210s 94.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.610s 255.579us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 95.530s 775.821us 1 1 100.00
rom_ctrl_tl_intg_err 39.680s 340.253us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 95.530s 775.821us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 95.530s 775.821us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 95.530s 775.821us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 95.530s 775.821us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.030s 425.909us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.030s 425.909us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.030s 425.909us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 39.680s 340.253us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
rom_ctrl_kmac_err_chk 5.080s 393.598us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.780s 8452.038us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.610s 255.579us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 95.530s 775.821us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 110.490s 38429.762us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 94758284397713290880568461335529058441821032298667569863748752510361332089436 85
UVM_INFO @ 9404364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---