Simulation Results: rom_ctrl/64kb

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.26 %
  • code
  • 91.29 %
  • assert
  • 97.39 %
  • func
  • 97.11 %
  • line
  • 98.81 %
  • branch
  • 98.18 %
  • cond
  • 97.62 %
  • toggle
  • 95.19 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.240s 726.126us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.400s 100.981us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.270s 145.916us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.190s 94.327us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.380s 91.452us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.300s 77.949us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.270s 145.916us 1 1 100.00
rom_ctrl_csr_aliasing 3.380s 91.452us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.600s 55.252us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.920s 67.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 8.830s 326.099us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.930s 83.926us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.500s 55.448us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.040s 58.570us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.400s 651.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.400s 651.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.400s 100.981us 1 1 100.00
rom_ctrl_csr_rw 3.270s 145.916us 1 1 100.00
rom_ctrl_csr_aliasing 3.380s 91.452us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.280s 94.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.400s 100.981us 1 1 100.00
rom_ctrl_csr_rw 3.270s 145.916us 1 1 100.00
rom_ctrl_csr_aliasing 3.380s 91.452us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.280s 94.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.750s 199.647us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 223.660s 243.515us 1 1 100.00
rom_ctrl_tl_intg_err 94.130s 1018.764us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 223.660s 243.515us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 223.660s 243.515us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 223.660s 243.515us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 223.660s 243.515us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.240s 726.126us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.240s 726.126us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.240s 726.126us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 94.130s 1018.764us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
rom_ctrl_kmac_err_chk 5.500s 55.448us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.280s 4656.909us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.750s 199.647us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 223.660s 243.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 12.790s 766.813us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 49865467379113538135216197054565211840790172302457111837652514549742412025959 85
UVM_INFO @ 326098962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---