Simulation Results: rstmgr

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.57 %
  • code
  • 99.30 %
  • assert
  • 98.66 %
  • func
  • 97.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.03 %
  • toggle
  • 98.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.340s 295.110us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.820s 110.073us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.940s 85.316us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.500s 702.489us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.840s 399.535us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.180s 123.245us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.940s 85.316us 1 1 100.00
rstmgr_csr_aliasing 1.840s 399.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.810s 114.166us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.370s 534.252us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.300s 160.875us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.560s 1114.203us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.560s 1114.203us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.560s 1114.203us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.560s 1114.203us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 20.300s 7201.079us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.800s 79.533us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.000s 431.525us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.000s 431.525us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.820s 110.073us 1 1 100.00
rstmgr_csr_rw 0.940s 85.316us 1 1 100.00
rstmgr_csr_aliasing 1.840s 399.535us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 135.816us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.820s 110.073us 1 1 100.00
rstmgr_csr_rw 0.940s 85.316us 1 1 100.00
rstmgr_csr_aliasing 1.840s 399.535us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 135.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.050s 8745.524us 1 1 100.00
rstmgr_tl_intg_err 1.650s 448.918us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.050s 8745.524us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.050s 8745.524us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.650s 448.918us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.000s 203.612us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.380s 1409.752us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.150s 303.694us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.050s 8745.524us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.940s 85.316us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.940s 85.316us 1 1 100.00