Simulation Results: rv_timer

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.62 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 96.47 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.770s 139.046us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 68.626us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.570s 41.402us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.210s 613.226us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.840s 147.577us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.640s 34.539us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.570s 41.402us 1 1 100.00
rv_timer_csr_aliasing 0.840s 147.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.680s 56.481us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.470s 1109.253us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 263.300s 993270.094us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 263.300s 993270.094us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.350s 2606.159us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 23.574us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 32.008us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.240s 180.587us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.240s 180.587us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 68.626us 1 1 100.00
rv_timer_csr_rw 0.570s 41.402us 1 1 100.00
rv_timer_csr_aliasing 0.840s 147.577us 1 1 100.00
rv_timer_same_csr_outstanding 0.770s 69.467us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 68.626us 1 1 100.00
rv_timer_csr_rw 0.570s 41.402us 1 1 100.00
rv_timer_csr_aliasing 0.840s 147.577us 1 1 100.00
rv_timer_same_csr_outstanding 0.770s 69.467us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.800s 104.870us 1 1 100.00
rv_timer_tl_intg_err 0.950s 128.043us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.950s 128.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.790s 1027.842us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.780s 472.917us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 29.030s 6897.420us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 1940735851230180543756727290253422160758534250233286058044453080013768429058 83
UVM_INFO @ 1027841923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 2957619725522274620085880958782235067914204703863848665856852232591456218229 81
UVM_INFO @ 472916817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---