Simulation Results: spi_device/1r1w

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.77 %
  • code
  • 91.39 %
  • assert
  • 95.40 %
  • func
  • 67.51 %
  • line
  • 98.86 %
  • branch
  • 98.21 %
  • cond
  • 96.22 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 85.220s 22029.618us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.890s 57.646us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.100s 68.780us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 17.570s 1962.577us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.760s 687.098us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.630s 141.271us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.100s 68.780us 1 1 100.00
spi_device_csr_aliasing 5.760s 687.098us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.710s 38.384us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 0.940s 29.521us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.740s 49.188us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.800s 4.126us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.670s 5.649us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.130s 86.430us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.130s 86.430us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.490s 6478.852us 1 1 100.00
spi_device_tpm_sts_read 1.090s 233.997us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 0.900s 24.968us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.580s 32.953us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.930s 65929.166us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.930s 65929.166us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.230s 821.212us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.230s 821.212us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.230s 821.212us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.230s 821.212us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.230s 821.212us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.740s 11513.281us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.920s 538.913us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.920s 538.913us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.920s 538.913us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 13.610s 1795.218us 1 1 100.00
spi_device_read_buffer_direct 3.160s 196.850us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.920s 538.913us 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 55.320s 14181.661us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.640s 2121.984us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.640s 2121.984us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 4.860s 774.933us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 85.220s 22029.618us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 59.310s 55514.131us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 283.560s 253051.055us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.710s 175.963us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.840s 14.983us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.050s 86.412us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.050s 86.412us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.890s 57.646us 1 1 100.00
spi_device_csr_rw 1.100s 68.780us 1 1 100.00
spi_device_csr_aliasing 5.760s 687.098us 1 1 100.00
spi_device_same_csr_outstanding 1.300s 43.455us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.890s 57.646us 1 1 100.00
spi_device_csr_rw 1.100s 68.780us 1 1 100.00
spi_device_csr_aliasing 5.760s 687.098us 1 1 100.00
spi_device_same_csr_outstanding 1.300s 43.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.970s 294.156us 1 1 100.00
spi_device_tl_intg_err 11.340s 305.761us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.340s 305.761us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 74779809140833031346068763042383614431080287236888523796182461685542785614186 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3298349 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3298349 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[976])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 104283768237799009540085547449290644980511359731940136195171641002264690993973 76
UVM_ERROR @ 3233068 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x181 [110000001] vs 0x0 [0])
UVM_ERROR @ 3274068 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1c5 [111000101] vs 0x0 [0])
UVM_ERROR @ 3324068 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x259 [1001011001] vs 0x0 [0])
UVM_ERROR @ 3355068 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x27a [1001111010] vs 0x0 [0])