Simulation Results: spi_host

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.74 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 95.000s 21176.237us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 63.056us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 18.715us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 1782.313us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 31.026us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 45.943us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 18.715us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.026us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.980us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 41.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 72.840us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 9.000s 2284.977us 1 1 100.00
spi_host_error_cmd 1.000s 20.025us 1 1 100.00
spi_host_event 12.000s 2063.885us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 216.726us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 216.726us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 216.726us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 66.000s 4209.528us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 71.334us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 29.316us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 216.726us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 216.726us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 95.000s 21176.237us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 95.000s 21176.237us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 82.542us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 3403.112us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 29.000s 3393.383us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 18.000s 1530.365us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 9.000s 2284.977us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 74.858us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 21.517us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 1663.189us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 1663.189us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 63.056us 1 1 100.00
spi_host_csr_rw 1.000s 18.715us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.026us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 24.137us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 63.056us 1 1 100.00
spi_host_csr_rw 1.000s 18.715us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.026us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 24.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 355.040us 1 1 100.00
spi_host_sec_cm 1.000s 126.522us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 355.040us 1 1 100.00