Simulation Results: sram_ctrl/main

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.67 %
  • code
  • 94.38 %
  • assert
  • 97.83 %
  • func
  • 91.80 %
  • block
  • 94.34 %
  • line
  • 94.75 %
  • branch
  • 90.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1417.123us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 24.466us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 10.398us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 867.835us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 2620.292us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 10.398us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.947us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 180.000s 6094.133us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 94.000s 4747.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 19.000s 13735.856us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 118.000s 16195.828us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 120.000s 17792.250us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 43.000s 10544.507us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 8.000s 6803.659us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 21.000s 39808.423us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 348.847us 1 1 100.00
sram_ctrl_partial_access_b2b 140.000s 10657.104us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 2668.548us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 744.678us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 686.800us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 407.216us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 366.093us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 100.000s 133876.090us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 45.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 39.078us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 39.078us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.466us 1 1 100.00
sram_ctrl_csr_rw 1.000s 10.398us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.947us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 18.481us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.466us 1 1 100.00
sram_ctrl_csr_rw 1.000s 10.398us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.947us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 18.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 6395.912us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 740.877us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 176.501us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 740.877us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 176.501us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 407.216us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 407.216us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 10.398us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 21.000s 39808.423us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 39808.423us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 39808.423us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 8.000s 6803.659us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 6653.821us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 6395.912us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 705.480us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1417.123us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1417.123us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 21.000s 39808.423us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 740.877us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 8.000s 6803.659us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 740.877us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 740.877us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1417.123us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 740.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 270.929us 1 1 100.00