Simulation Results: sysrst_ctrl

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.18 %
  • code
  • 94.10 %
  • assert
  • 96.07 %
  • func
  • 65.38 %
  • line
  • 97.92 %
  • branch
  • 97.85 %
  • cond
  • 95.23 %
  • toggle
  • 100.00 %
  • FSM
  • 79.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.550s 2123.699us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.710s 2472.230us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.400s 2180.672us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.230s 2551.196us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 9.510s 6033.717us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.020s 2053.487us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 20.200s 36849.278us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.450s 2396.801us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.720s 2116.203us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.020s 2053.487us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.450s 2396.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 7.800s 37328.664us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 91.410s 52524.046us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.910s 3629.064us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.770s 2652.043us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.680s 2514.570us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.250s 2089.183us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.900s 3178.577us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.110s 2617.000us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.040s 3159.672us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 62.580s 38802.572us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.280s 10862.101us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.140s 2040.723us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.710s 2015.681us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.350s 2055.077us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.350s 2055.077us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.510s 6033.717us 1 1 100.00
sysrst_ctrl_csr_rw 4.020s 2053.487us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.450s 2396.801us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.930s 4629.101us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.510s 6033.717us 1 1 100.00
sysrst_ctrl_csr_rw 4.020s 2053.487us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.450s 2396.801us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.930s 4629.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 8.570s 22180.278us 1 1 100.00
sysrst_ctrl_tl_intg_err 76.840s 42411.376us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 76.840s 42411.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.860s 9446.477us 1 1 100.00