Simulation Results: uart

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.10 %
  • code
  • 92.55 %
  • assert
  • 98.27 %
  • func
  • 64.47 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.90 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.240s 319.429us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.610s 14.624us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 49.938us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.780s 81.044us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.730s 21.908us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.790s 21.313us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 49.938us 1 1 100.00
uart_csr_aliasing 0.730s 21.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 30.360s 140601.782us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.240s 319.429us 1 1 100.00
uart_tx_rx 30.360s 140601.782us 1 1 100.00
parity_error 2 2 100.00
uart_intr 4.180s 21164.522us 1 1 100.00
uart_rx_parity_err 4.440s 35627.431us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 30.360s 140601.782us 1 1 100.00
uart_intr 4.180s 21164.522us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 21.200s 114102.188us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 153.590s 163741.019us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 56.120s 57309.709us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 4.180s 21164.522us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 4.180s 21164.522us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 4.180s 21164.522us 1 1 100.00
perf 1 1 100.00
uart_perf 110.720s 8922.575us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.730s 11696.081us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.730s 11696.081us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 11.340s 10509.755us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.700s 47481.383us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.020s 588.994us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 16.570s 4152.510us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 393.910s 82520.237us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 57.650s 206648.929us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.630s 12.054us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 19.802us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 0.950s 43.667us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 0.950s 43.667us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.610s 14.624us 1 1 100.00
uart_csr_rw 0.590s 49.938us 1 1 100.00
uart_csr_aliasing 0.730s 21.908us 1 1 100.00
uart_same_csr_outstanding 0.740s 101.959us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.610s 14.624us 1 1 100.00
uart_csr_rw 0.590s 49.938us 1 1 100.00
uart_csr_aliasing 0.730s 21.908us 1 1 100.00
uart_same_csr_outstanding 0.740s 101.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 210.971us 1 1 100.00
uart_tl_intg_err 1.150s 385.541us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.150s 385.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 17.220s 1996.193us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 109035872020313712646764629648903854472185822039231259549821373557670694166758 85
UVM_ERROR @ 10072415123 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 10072435123 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 10072495123 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (216 [0xd8] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 10088255123 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0