Simulation Results: adc_ctrl

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.17 %
  • code
  • 97.90 %
  • assert
  • 96.60 %
  • func
  • 19.01 %
  • line
  • 99.02 %
  • branch
  • 98.45 %
  • cond
  • 94.71 %
  • toggle
  • 100.00 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.430s 5968.552us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.770s 1340.383us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.930s 362.867us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 28.990s 48875.512us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.370s 820.630us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.110s 524.271us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.930s 362.867us 1 1 100.00
adc_ctrl_csr_aliasing 1.370s 820.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 12.910s 19178.673us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 35.610s 51931.896us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 51.330s 36660.434us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 20.640s 55081.978us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 66.240s 53248.809us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 102.030s 71564.826us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 53.070s 40682.604us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 10.600s 40820.204us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 4.510s 2771.345us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 32.750s 44019.668us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 45.250s 119061.021us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 182.160s 274084.533us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.680s 489.431us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.720s 391.741us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.640s 376.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.640s 376.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.770s 1340.383us 1 1 100.00
adc_ctrl_csr_rw 0.930s 362.867us 1 1 100.00
adc_ctrl_csr_aliasing 1.370s 820.630us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.620s 2113.067us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.770s 1340.383us 1 1 100.00
adc_ctrl_csr_rw 0.930s 362.867us 1 1 100.00
adc_ctrl_csr_aliasing 1.370s 820.630us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.620s 2113.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.500s 8626.517us 1 1 100.00
adc_ctrl_tl_intg_err 2.900s 4644.002us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.900s 4644.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 8.650s 4064.884us 1 1 100.00